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Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [clkgen/] [clkgen.v] - Diff between revs 362 and 363

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Rev 362 Rev 363
Line 41... Line 41...
module clkgen
module clkgen
  (
  (
   // Main clocks in, depending on board
   // Main clocks in, depending on board
   clk_pad_i,
   clk_pad_i,
 
 
 
   // Input reset - through a buffer, asynchronous
 
   async_rst_o,
   // Wishbone clock and reset out  
   // Wishbone clock and reset out  
   wb_clk_o,
   wb_clk_o,
   wb_rst_o,
   wb_rst_o,
 
 
   // JTAG clock
   // JTAG clock
Line 58... Line 60...
 
 
   );
   );
 
 
   input clk_pad_i;
   input clk_pad_i;
 
 
 
   output async_rst_o;
 
 
   output wb_rst_o;
   output wb_rst_o;
   output wb_clk_o;
   output wb_clk_o;
 
 
`ifdef JTAG_DEBUG
`ifdef JTAG_DEBUG
   input  tck_pad_i;
   input  tck_pad_i;
Line 70... Line 74...
 
 
   // Asynchronous, active low reset (pushbutton, typically)
   // Asynchronous, active low reset (pushbutton, typically)
   input  rst_n_pad_i;
   input  rst_n_pad_i;
 
 
   // First, deal with the asychronous reset
   // First, deal with the asychronous reset
   wire   async_rst;
 
   wire   async_rst_n;
   wire   async_rst_n;
 
 
   // An input buffer is usually instantiated here
   // An input buffer is usually instantiated here
   assign async_rst_n = rst_n_pad_i;
   assign async_rst_n = rst_n_pad_i;
 
 
   // Everyone likes active-high reset signals...
   // Everyone likes active-high reset signals...
   assign async_rst = ~async_rst_n;
   assign async_rst_o = ~async_rst_n;
 
 
`ifdef JTAG_DEBUG
`ifdef JTAG_DEBUG
   assign dbg_tck_o = tck_pad_i;
   assign dbg_tck_o = tck_pad_i;
`endif
`endif
 
 
Line 102... Line 105...
   //
   //
   //
   //
 
 
   // Reset generation for wishbone
   // Reset generation for wishbone
   reg [15:0]       wb_rst_shr;
   reg [15:0]       wb_rst_shr;
   always @(posedge wb_clk_o or posedge async_rst)
   always @(posedge wb_clk_o or posedge async_rst_o)
     if (async_rst)
     if (async_rst_o)
       wb_rst_shr <= 16'hffff;
       wb_rst_shr <= 16'hffff;
     else
     else
       wb_rst_shr <= {wb_rst_shr[14:0], ~(sync_rst_n)};
       wb_rst_shr <= {wb_rst_shr[14:0], ~(sync_rst_n)};
 
 
   assign wb_rst_o = wb_rst_shr[15];
   assign wb_rst_o = wb_rst_shr[15];

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