Subversion Repositories openrisc_me

module clkgen

module clkgen

  (

  (

   // Main clocks in, depending on board

   // Main clocks in, depending on board

   clk_pad_i,

   clk_pad_i,

   // Wishbone clock and reset out  

   // Wishbone clock and reset out  

   wb_clk_o,

   wb_clk_o,

   wb_rst_o,

   wb_rst_o,

   // JTAG clock

   // JTAG clock

   );

   );

   input clk_pad_i;

   input clk_pad_i;

   output wb_rst_o;

   output wb_rst_o;

   output wb_clk_o;

   output wb_clk_o;

`ifdef JTAG_DEBUG

`ifdef JTAG_DEBUG

   input  tck_pad_i;

   input  tck_pad_i;

   // Asynchronous, active low reset (pushbutton, typically)

   // Asynchronous, active low reset (pushbutton, typically)

   input  rst_n_pad_i;

   input  rst_n_pad_i;

   // First, deal with the asychronous reset

   // First, deal with the asychronous reset

   wire   async_rst_n;

   wire   async_rst_n;

   // An input buffer is usually instantiated here

   // An input buffer is usually instantiated here

   assign async_rst_n = rst_n_pad_i;

   assign async_rst_n = rst_n_pad_i;

   // Everyone likes active-high reset signals...

   // Everyone likes active-high reset signals...

`ifdef JTAG_DEBUG

`ifdef JTAG_DEBUG

   assign dbg_tck_o = tck_pad_i;

   assign dbg_tck_o = tck_pad_i;

`endif

`endif

   //

   //

   //

   //

   // Reset generation for wishbone

   // Reset generation for wishbone

   reg [15:0]       wb_rst_shr;

   reg [15:0]       wb_rst_shr;

       wb_rst_shr <= 16'hffff;

       wb_rst_shr <= 16'hffff;

     else

     else

       wb_rst_shr <= {wb_rst_shr[14:0], ~(sync_rst_n)};

       wb_rst_shr <= {wb_rst_shr[14:0], ~(sync_rst_n)};

   assign wb_rst_o = wb_rst_shr[15];

   assign wb_rst_o = wb_rst_shr[15];