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//////////////////////////////////////////////////////////////////////
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//// ////
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//// dbg_cpu.v ////
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//// ////
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//// ////
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//// This file is part of the SoC Debug Interface. ////
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//// http://www.opencores.org/projects/DebugInterface/ ////
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//// ////
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//// Author(s): ////
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//// Igor Mohor (igorm@opencores.org) ////
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//// ////
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//// ////
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//// All additional information is avaliable in the README.txt ////
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//// file. ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2000 - 2004 Authors ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: dbg_cpu.v,v $
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// Revision 1.12 2004/04/08 14:15:10 igorm
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// CTRL READ fixed. Stall bit was not shifted out OK. Error appeared in last
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// check-in.
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//
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// Revision 1.11 2004/04/07 19:28:55 igorm
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// Zero is shifted out when CTRL_READ command is active.
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//
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// Revision 1.10 2004/04/01 10:22:45 igorm
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// Signals for easier debugging removed.
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//
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// Revision 1.9 2004/03/31 14:34:09 igorm
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// data_cnt_lim length changed to reduce number of warnings.
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//
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// Revision 1.8 2004/03/28 20:27:01 igorm
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// New release of the debug interface (3rd. release).
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//
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// Revision 1.7 2004/01/25 14:04:18 mohor
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// All flipflops are reset.
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//
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// Revision 1.6 2004/01/22 13:58:53 mohor
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// Port signals are all set to zero after reset.
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//
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// Revision 1.5 2004/01/19 07:32:41 simons
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// Reset values width added because of FV, a good sentence changed because some tools can not handle it.
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//
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// Revision 1.4 2004/01/17 18:38:11 mohor
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// cpu_tall_o is set with cpu_stb_o or register.
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//
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// Revision 1.3 2004/01/17 18:01:24 mohor
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// New version.
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//
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// Revision 1.2 2004/01/17 17:01:14 mohor
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// Almost finished.
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//
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// Revision 1.1 2004/01/16 14:53:31 mohor
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// *** empty log message ***
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//
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//
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//
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// synopsys translate_off
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`include "timescale.v"
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// synopsys translate_on
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`include "dbg_cpu_defines.v"
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// Top module
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module dbg_cpu(
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// JTAG signals
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tck_i,
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tdi_i,
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tdo_o,
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// TAP states
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shift_dr_i,
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pause_dr_i,
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update_dr_i,
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cpu_ce_i,
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crc_match_i,
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crc_en_o,
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shift_crc_o,
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rst_i,
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// CPU
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cpu_clk_i,
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cpu_addr_o, cpu_data_i, cpu_data_o, cpu_bp_i, cpu_stall_o,
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cpu_stb_o,
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cpu_we_o, cpu_ack_i, cpu_rst_o
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);
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// JTAG signals
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input tck_i;
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input tdi_i;
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output tdo_o;
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// TAP states
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input shift_dr_i;
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input pause_dr_i;
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input update_dr_i;
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input cpu_ce_i;
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input crc_match_i;
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output crc_en_o;
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output shift_crc_o;
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input rst_i;
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// CPU
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input cpu_clk_i;
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output [31:0] cpu_addr_o;
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output [31:0] cpu_data_o;
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input cpu_bp_i;
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output cpu_stall_o;
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input [31:0] cpu_data_i;
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output cpu_stb_o;
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output cpu_we_o;
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input cpu_ack_i;
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output cpu_rst_o;
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reg cpu_stb_o;
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wire cpu_reg_stall;
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reg tdo_o;
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reg cpu_ack_q;
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reg cpu_ack_csff;
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reg cpu_ack_tck;
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reg [31:0] cpu_dat_tmp, cpu_data_dsff;
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reg [31:0] cpu_addr_dsff;
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reg cpu_we_dsff;
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reg [`DBG_CPU_DR_LEN -1 :0] dr;
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wire enable;
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wire cmd_cnt_en;
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reg [`DBG_CPU_CMD_CNT_WIDTH -1:0] cmd_cnt;
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wire cmd_cnt_end;
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reg cmd_cnt_end_q;
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reg addr_len_cnt_en;
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reg [5:0] addr_len_cnt;
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wire addr_len_cnt_end;
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reg addr_len_cnt_end_q;
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reg crc_cnt_en;
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reg [`DBG_CPU_CRC_CNT_WIDTH -1:0] crc_cnt;
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wire crc_cnt_end;
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reg crc_cnt_end_q;
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reg data_cnt_en;
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reg [`DBG_CPU_DATA_CNT_WIDTH:0] data_cnt;
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reg [`DBG_CPU_DATA_CNT_LIM_WIDTH:0] data_cnt_limit;
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wire data_cnt_end;
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reg data_cnt_end_q;
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reg crc_match_reg;
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reg [`DBG_CPU_ACC_TYPE_LEN -1:0] acc_type;
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reg [`DBG_CPU_ADR_LEN -1:0] adr;
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reg [`DBG_CPU_LEN_LEN -1:0] len;
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reg [`DBG_CPU_LEN_LEN:0] len_var;
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wire [`DBG_CPU_CTRL_LEN -1:0]ctrl_reg;
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reg start_rd_tck;
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reg rd_tck_started;
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reg start_rd_csff;
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reg start_cpu_rd;
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reg start_cpu_rd_q;
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reg start_wr_tck;
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reg start_wr_csff;
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reg start_cpu_wr;
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reg start_cpu_wr_q;
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reg status_cnt_en;
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wire status_cnt_end;
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wire half, long;
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reg half_q, long_q;
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reg [`DBG_CPU_STATUS_CNT_WIDTH -1:0] status_cnt;
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reg [`DBG_CPU_STATUS_LEN -1:0] status;
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reg cpu_overrun, cpu_overrun_csff, cpu_overrun_tck;
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reg underrun_tck;
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reg busy_cpu;
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reg busy_tck;
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reg cpu_end;
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reg cpu_end_rst;
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reg cpu_end_rst_csff;
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reg cpu_end_csff;
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reg cpu_end_tck, cpu_end_tck_q;
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reg busy_csff;
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reg latch_data;
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reg update_dr_csff, update_dr_cpu;
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wire [`DBG_CPU_CTRL_LEN -1:0] cpu_reg_data_i;
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wire cpu_reg_we;
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reg set_addr, set_addr_csff, set_addr_cpu, set_addr_cpu_q;
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wire [31:0] input_data;
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wire len_eq_0;
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wire crc_cnt_31;
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reg fifo_full;
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reg [7:0] mem [0:3];
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reg cpu_ce_csff;
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reg mem_ptr_init;
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reg [`DBG_CPU_CMD_LEN -1: 0] curr_cmd;
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wire curr_cmd_go;
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reg curr_cmd_go_q;
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wire curr_cmd_wr_comm;
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wire curr_cmd_wr_ctrl;
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wire curr_cmd_rd_comm;
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wire curr_cmd_rd_ctrl;
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wire acc_type_read;
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wire acc_type_write;
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assign enable = cpu_ce_i & shift_dr_i;
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assign crc_en_o = enable & crc_cnt_end & (~status_cnt_end);
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assign shift_crc_o = enable & status_cnt_end; // Signals dbg module to shift out the CRC
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assign curr_cmd_go = (curr_cmd == `DBG_CPU_GO) && cmd_cnt_end;
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assign curr_cmd_wr_comm = (curr_cmd == `DBG_CPU_WR_COMM) && cmd_cnt_end;
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assign curr_cmd_wr_ctrl = (curr_cmd == `DBG_CPU_WR_CTRL) && cmd_cnt_end;
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assign curr_cmd_rd_comm = (curr_cmd == `DBG_CPU_RD_COMM) && cmd_cnt_end;
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assign curr_cmd_rd_ctrl = (curr_cmd == `DBG_CPU_RD_CTRL) && cmd_cnt_end;
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assign acc_type_read = (acc_type == `DBG_CPU_READ);
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assign acc_type_write = (acc_type == `DBG_CPU_WRITE);
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// Shift register for shifting in and out the data
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always @ (posedge tck_i or posedge rst_i)
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begin
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if (rst_i)
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begin
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latch_data <= 1'b0;
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dr <= {`DBG_CPU_DR_LEN{1'b0}};
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end
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else if (curr_cmd_rd_comm && crc_cnt_31) // Latching data (from internal regs)
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begin
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dr[`DBG_CPU_DR_LEN -1:0] <= {acc_type, adr, len};
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end
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else if (curr_cmd_rd_ctrl && crc_cnt_31) // Latching data (from control regs)
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begin
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dr[`DBG_CPU_DR_LEN -1:0] <= {ctrl_reg, {`DBG_CPU_DR_LEN -`DBG_CPU_CTRL_LEN{1'b0}}};
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end
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else if (acc_type_read && curr_cmd_go && crc_cnt_31) // Latchind first data (from WB)
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begin
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dr[31:0] <= input_data[31:0];
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latch_data <= 1'b1;
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end
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else if (acc_type_read && curr_cmd_go && crc_cnt_end) // Latching data (from WB)
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begin
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case (acc_type) // synthesis parallel_case full_case
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`DBG_CPU_READ: begin
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if(long & (~long_q))
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begin
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dr[31:0] <= input_data[31:0];
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latch_data <= 1'b1;
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end
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else if (enable)
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begin
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dr[31:0] <= {dr[30:0], 1'b0};
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latch_data <= 1'b0;
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end
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end
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endcase
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end
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else if (enable && (!addr_len_cnt_end))
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begin
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dr <= {dr[`DBG_CPU_DR_LEN -2:0], tdi_i};
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end
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end
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assign cmd_cnt_en = enable & (~cmd_cnt_end);
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// Command counter
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always @ (posedge tck_i or posedge rst_i)
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begin
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if (rst_i)
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cmd_cnt <= {`DBG_CPU_CMD_CNT_WIDTH{1'b0}};
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else if (update_dr_i)
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cmd_cnt <= {`DBG_CPU_CMD_CNT_WIDTH{1'b0}};
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else if (cmd_cnt_en)
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cmd_cnt <= cmd_cnt + 1'b1;
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end
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// Assigning current command
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always @ (posedge tck_i or posedge rst_i)
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begin
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if (rst_i)
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curr_cmd <= {`DBG_CPU_CMD_LEN{1'b0}};
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else if (update_dr_i)
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curr_cmd <= {`DBG_CPU_CMD_LEN{1'b0}};
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else if (cmd_cnt == (`DBG_CPU_CMD_LEN -1))
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curr_cmd <= {dr[`DBG_CPU_CMD_LEN-2 :0], tdi_i};
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end
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// Assigning current command
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always @ (posedge tck_i or posedge rst_i)
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begin
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if (rst_i)
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curr_cmd_go_q <= 1'b0;
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else
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curr_cmd_go_q <= curr_cmd_go;
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end
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always @ (enable or cmd_cnt_end or addr_len_cnt_end or curr_cmd_wr_comm or curr_cmd_wr_ctrl or curr_cmd_rd_comm or curr_cmd_rd_ctrl or crc_cnt_end)
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begin
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if (enable && (!addr_len_cnt_end))
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begin
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if (cmd_cnt_end && (curr_cmd_wr_comm || curr_cmd_wr_ctrl))
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addr_len_cnt_en = 1'b1;
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else if (crc_cnt_end && (curr_cmd_rd_comm || curr_cmd_rd_ctrl))
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addr_len_cnt_en = 1'b1;
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else
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addr_len_cnt_en = 1'b0;
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end
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else
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addr_len_cnt_en = 1'b0;
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end
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// Address/length counter
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always @ (posedge tck_i or posedge rst_i)
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begin
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if (rst_i)
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addr_len_cnt <= 6'h0;
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else if (update_dr_i)
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addr_len_cnt <= 6'h0;
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else if (addr_len_cnt_en)
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addr_len_cnt <= addr_len_cnt + 1'b1;
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end
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always @ (enable or data_cnt_end or cmd_cnt_end or curr_cmd_go or acc_type_write or acc_type_read or crc_cnt_end)
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begin
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if (enable && (!data_cnt_end))
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begin
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if (cmd_cnt_end && curr_cmd_go && acc_type_write)
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data_cnt_en = 1'b1;
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else if (crc_cnt_end && curr_cmd_go && acc_type_read)
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data_cnt_en = 1'b1;
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else
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data_cnt_en = 1'b0;
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end
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else
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data_cnt_en = 1'b0;
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end
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// Data counter
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always @ (posedge tck_i or posedge rst_i)
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begin
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if (rst_i)
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data_cnt <= {`DBG_CPU_DATA_CNT_WIDTH{1'b0}};
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else if (update_dr_i)
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data_cnt <= {`DBG_CPU_DATA_CNT_WIDTH{1'b0}};
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else if (data_cnt_en)
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data_cnt <= data_cnt + 1'b1;
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end
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// Upper limit. Data counter counts until this value is reached.
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always @ (posedge tck_i or posedge rst_i)
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begin
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if (rst_i)
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data_cnt_limit <= {`DBG_CPU_DATA_CNT_LIM_WIDTH{1'b0}};
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else if (update_dr_i)
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data_cnt_limit <= len + 1'b1;
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end
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always @ (enable or crc_cnt_end or curr_cmd_rd_comm or curr_cmd_rd_ctrl or curr_cmd_wr_comm or curr_cmd_wr_ctrl or curr_cmd_go or addr_len_cnt_end or data_cnt_end or acc_type_write or acc_type_read or cmd_cnt_end)
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begin
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if (enable && (!crc_cnt_end) && cmd_cnt_end)
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begin
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if (addr_len_cnt_end && (curr_cmd_wr_comm || curr_cmd_wr_ctrl))
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crc_cnt_en = 1'b1;
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else if (data_cnt_end && curr_cmd_go && acc_type_write)
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crc_cnt_en = 1'b1;
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else if (cmd_cnt_end && (curr_cmd_go && acc_type_read || curr_cmd_rd_comm || curr_cmd_rd_ctrl))
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crc_cnt_en = 1'b1;
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else
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crc_cnt_en = 1'b0;
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end
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else
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crc_cnt_en = 1'b0;
|
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end
|
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|
|
|
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// crc counter
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always @ (posedge tck_i or posedge rst_i)
|
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begin
|
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if (rst_i)
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crc_cnt <= {`DBG_CPU_CRC_CNT_WIDTH{1'b0}};
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else if(crc_cnt_en)
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crc_cnt <= crc_cnt + 1'b1;
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else if (update_dr_i)
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crc_cnt <= {`DBG_CPU_CRC_CNT_WIDTH{1'b0}};
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end
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assign cmd_cnt_end = cmd_cnt == `DBG_CPU_CMD_LEN;
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assign addr_len_cnt_end = addr_len_cnt == `DBG_CPU_DR_LEN;
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assign crc_cnt_end = crc_cnt == `DBG_CPU_CRC_CNT_WIDTH'd32;
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assign crc_cnt_31 = crc_cnt == `DBG_CPU_CRC_CNT_WIDTH'd31;
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assign data_cnt_end = (data_cnt == {data_cnt_limit, 3'b000});
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always @ (posedge tck_i or posedge rst_i)
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begin
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if (rst_i)
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begin
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crc_cnt_end_q <= 1'b0;
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cmd_cnt_end_q <= 1'b0;
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data_cnt_end_q <= 1'b0;
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addr_len_cnt_end_q <= 1'b0;
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end
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else
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begin
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crc_cnt_end_q <= crc_cnt_end;
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cmd_cnt_end_q <= cmd_cnt_end;
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data_cnt_end_q <= data_cnt_end;
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addr_len_cnt_end_q <= addr_len_cnt_end;
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end
|
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end
|
|
|
|
|
|
// Status counter is made of 4 serialy connected registers
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|
always @ (posedge tck_i or posedge rst_i)
|
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begin
|
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if (rst_i)
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status_cnt <= {`DBG_CPU_STATUS_CNT_WIDTH{1'b0}};
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else if (update_dr_i)
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status_cnt <= {`DBG_CPU_STATUS_CNT_WIDTH{1'b0}};
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else if (status_cnt_en)
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status_cnt <= status_cnt + 1'b1;
|
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end
|
|
|
|
|
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always @ (enable or status_cnt_end or crc_cnt_end or curr_cmd_rd_comm or curr_cmd_rd_ctrl or
|
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curr_cmd_wr_comm or curr_cmd_wr_ctrl or curr_cmd_go or acc_type_write or
|
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acc_type_read or data_cnt_end or addr_len_cnt_end)
|
|
begin
|
|
if (enable && (!status_cnt_end))
|
|
begin
|
|
if (crc_cnt_end && (curr_cmd_wr_comm || curr_cmd_wr_ctrl))
|
|
status_cnt_en = 1'b1;
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else if (crc_cnt_end && curr_cmd_go && acc_type_write)
|
|
status_cnt_en = 1'b1;
|
|
else if (data_cnt_end && curr_cmd_go && acc_type_read)
|
|
status_cnt_en = 1'b1;
|
|
else if (addr_len_cnt_end && (curr_cmd_rd_comm || curr_cmd_rd_ctrl))
|
|
status_cnt_en = 1'b1;
|
|
else
|
|
status_cnt_en = 1'b0;
|
|
end
|
|
else
|
|
status_cnt_en = 1'b0;
|
|
end
|
|
|
|
|
|
assign status_cnt_end = status_cnt == `DBG_CPU_STATUS_LEN;
|
|
|
|
|
|
// Latching acc_type, address and length
|
|
always @ (posedge tck_i or posedge rst_i)
|
|
begin
|
|
if (rst_i)
|
|
begin
|
|
acc_type <= {`DBG_CPU_ACC_TYPE_LEN{1'b0}};
|
|
adr <= {`DBG_CPU_ADR_LEN{1'b0}};
|
|
len <= {`DBG_CPU_LEN_LEN{1'b0}};
|
|
set_addr <= 1'b0;
|
|
end
|
|
else if(crc_cnt_end && (!crc_cnt_end_q) && crc_match_i && curr_cmd_wr_comm)
|
|
begin
|
|
acc_type <= dr[`DBG_CPU_ACC_TYPE_LEN + `DBG_CPU_ADR_LEN + `DBG_CPU_LEN_LEN -1 : `DBG_CPU_ADR_LEN + `DBG_CPU_LEN_LEN];
|
|
adr <= dr[`DBG_CPU_ADR_LEN + `DBG_CPU_LEN_LEN -1 : `DBG_CPU_LEN_LEN];
|
|
len <= dr[`DBG_CPU_LEN_LEN -1:0];
|
|
set_addr <= 1'b1;
|
|
end
|
|
else if(cpu_end_tck) // Writing back the address
|
|
begin
|
|
adr <= cpu_addr_dsff;
|
|
end
|
|
else
|
|
set_addr <= 1'b0;
|
|
end
|
|
|
|
|
|
always @ (posedge tck_i or posedge rst_i)
|
|
begin
|
|
if (rst_i)
|
|
crc_match_reg <= 1'b0;
|
|
else if(crc_cnt_end & (~crc_cnt_end_q))
|
|
crc_match_reg <= crc_match_i;
|
|
end
|
|
|
|
|
|
// Length counter
|
|
always @ (posedge tck_i or posedge rst_i)
|
|
begin
|
|
if (rst_i)
|
|
len_var <= {1'b0, {`DBG_CPU_LEN_LEN{1'b0}}};
|
|
else if(update_dr_i)
|
|
len_var <= len + 1'b1;
|
|
else if (start_rd_tck)
|
|
begin
|
|
if (len_var > 'd4)
|
|
len_var <= len_var - 3'd4;
|
|
else
|
|
len_var <= {1'b0, {`DBG_CPU_LEN_LEN{1'b0}}};
|
|
end
|
|
end
|
|
|
|
|
|
assign len_eq_0 = len_var == 'h0;
|
|
|
|
|
|
assign half = data_cnt[3:0] == 4'd15;
|
|
assign long = data_cnt[4:0] == 5'd31;
|
|
|
|
|
|
always @ (posedge tck_i or posedge rst_i)
|
|
begin
|
|
if (rst_i)
|
|
begin
|
|
half_q <= 1'b0;
|
|
long_q <= 1'b0;
|
|
end
|
|
else
|
|
begin
|
|
half_q <= half;
|
|
long_q <= long;
|
|
end
|
|
end
|
|
|
|
|
|
// Start cpu write cycle
|
|
always @ (posedge tck_i or posedge rst_i)
|
|
begin
|
|
if (rst_i)
|
|
begin
|
|
start_wr_tck <= 1'b0;
|
|
cpu_dat_tmp <= 32'h0;
|
|
end
|
|
else if (curr_cmd_go && acc_type_write)
|
|
begin
|
|
if (long_q)
|
|
begin
|
|
start_wr_tck <= 1'b1;
|
|
cpu_dat_tmp <= dr[31:0];
|
|
end
|
|
else
|
|
begin
|
|
start_wr_tck <= 1'b0;
|
|
end
|
|
end
|
|
else
|
|
start_wr_tck <= 1'b0;
|
|
end
|
|
|
|
|
|
// cpu_data_o in WB clk domain
|
|
always @ (posedge cpu_clk_i)
|
|
begin
|
|
cpu_data_dsff <= cpu_dat_tmp;
|
|
end
|
|
|
|
assign cpu_data_o = cpu_data_dsff;
|
|
|
|
|
|
// Start cpu read cycle
|
|
always @ (posedge tck_i or posedge rst_i)
|
|
begin
|
|
if (rst_i)
|
|
start_rd_tck <= 1'b0;
|
|
else if (curr_cmd_go && (!curr_cmd_go_q) && acc_type_read) // First read after cmd is entered
|
|
start_rd_tck <= 1'b1;
|
|
else if ((!start_rd_tck) && curr_cmd_go && acc_type_read && (!len_eq_0) && (!fifo_full) && (!rd_tck_started) && (!cpu_ack_tck))
|
|
start_rd_tck <= 1'b1;
|
|
else
|
|
start_rd_tck <= 1'b0;
|
|
end
|
|
|
|
|
|
always @ (posedge tck_i or posedge rst_i)
|
|
begin
|
|
if (rst_i)
|
|
rd_tck_started <= 1'b0;
|
|
else if (update_dr_i || cpu_end_tck && (!cpu_end_tck_q))
|
|
rd_tck_started <= 1'b0;
|
|
else if (start_rd_tck)
|
|
rd_tck_started <= 1'b1;
|
|
end
|
|
|
|
|
|
|
|
always @ (posedge cpu_clk_i or posedge rst_i)
|
|
begin
|
|
if (rst_i)
|
|
begin
|
|
start_rd_csff <= 1'b0;
|
|
start_cpu_rd <= 1'b0;
|
|
start_cpu_rd_q <= 1'b0;
|
|
|
|
start_wr_csff <= 1'b0;
|
|
start_cpu_wr <= 1'b0;
|
|
start_cpu_wr_q <= 1'b0;
|
|
|
|
set_addr_csff <= 1'b0;
|
|
set_addr_cpu <= 1'b0;
|
|
set_addr_cpu_q <= 1'b0;
|
|
|
|
cpu_ack_q <= 1'b0;
|
|
end
|
|
else
|
|
begin
|
|
start_rd_csff <= start_rd_tck;
|
|
start_cpu_rd <= start_rd_csff;
|
|
start_cpu_rd_q <= start_cpu_rd;
|
|
|
|
start_wr_csff <= start_wr_tck;
|
|
start_cpu_wr <= start_wr_csff;
|
|
start_cpu_wr_q <= start_cpu_wr;
|
|
|
|
set_addr_csff <= set_addr;
|
|
set_addr_cpu <= set_addr_csff;
|
|
set_addr_cpu_q <= set_addr_cpu;
|
|
|
|
cpu_ack_q <= cpu_ack_i;
|
|
end
|
|
end
|
|
|
|
|
|
// cpu_stb_o
|
|
always @ (posedge cpu_clk_i or posedge rst_i)
|
|
begin
|
|
if (rst_i)
|
|
cpu_stb_o <= 1'b0;
|
|
else if (cpu_ack_i)
|
|
cpu_stb_o <= 1'b0;
|
|
else if ((start_cpu_wr && (!start_cpu_wr_q)) || (start_cpu_rd && (!start_cpu_rd_q)))
|
|
cpu_stb_o <= 1'b1;
|
|
end
|
|
|
|
|
|
assign cpu_stall_o = cpu_stb_o | cpu_reg_stall;
|
|
|
|
|
|
// cpu_addr_o logic
|
|
always @ (posedge cpu_clk_i or posedge rst_i)
|
|
begin
|
|
if (rst_i)
|
|
cpu_addr_dsff <= 32'h0;
|
|
else if (set_addr_cpu && (!set_addr_cpu_q)) // Setting starting address
|
|
cpu_addr_dsff <= adr;
|
|
else if (cpu_ack_i && (!cpu_ack_q))
|
|
//cpu_addr_dsff <= cpu_addr_dsff + 3'd4;
|
|
cpu_addr_dsff <= cpu_addr_dsff + 3'd1; // Increment by just 1, to allow block reading -- jb 090901
|
|
end
|
|
|
|
|
|
assign cpu_addr_o = cpu_addr_dsff;
|
|
|
|
|
|
always @ (posedge cpu_clk_i)
|
|
begin
|
|
cpu_we_dsff <= curr_cmd_go && acc_type_write;
|
|
end
|
|
|
|
|
|
assign cpu_we_o = cpu_we_dsff;
|
|
|
|
|
|
|
|
// Logic for detecting end of transaction
|
|
always @ (posedge cpu_clk_i or posedge rst_i)
|
|
begin
|
|
if (rst_i)
|
|
cpu_end <= 1'b0;
|
|
else if (cpu_ack_i && (!cpu_ack_q))
|
|
cpu_end <= 1'b1;
|
|
else if (cpu_end_rst)
|
|
cpu_end <= 1'b0;
|
|
end
|
|
|
|
|
|
always @ (posedge tck_i or posedge rst_i)
|
|
begin
|
|
if (rst_i)
|
|
begin
|
|
cpu_end_csff <= 1'b0;
|
|
cpu_end_tck <= 1'b0;
|
|
cpu_end_tck_q <= 1'b0;
|
|
end
|
|
else
|
|
begin
|
|
cpu_end_csff <= cpu_end;
|
|
cpu_end_tck <= cpu_end_csff;
|
|
cpu_end_tck_q <= cpu_end_tck;
|
|
end
|
|
end
|
|
|
|
|
|
always @ (posedge cpu_clk_i or posedge rst_i)
|
|
begin
|
|
if (rst_i)
|
|
begin
|
|
cpu_end_rst_csff <= 1'b0;
|
|
cpu_end_rst <= 1'b0;
|
|
end
|
|
else
|
|
begin
|
|
cpu_end_rst_csff <= cpu_end_tck;
|
|
cpu_end_rst <= cpu_end_rst_csff;
|
|
end
|
|
end
|
|
|
|
|
|
always @ (posedge cpu_clk_i or posedge rst_i)
|
|
begin
|
|
if (rst_i)
|
|
busy_cpu <= 1'b0;
|
|
else if (cpu_end_rst)
|
|
busy_cpu <= 1'b0;
|
|
else if (cpu_stb_o)
|
|
busy_cpu <= 1'b1;
|
|
end
|
|
|
|
|
|
always @ (posedge tck_i or posedge rst_i)
|
|
begin
|
|
if (rst_i)
|
|
begin
|
|
busy_csff <= 1'b0;
|
|
busy_tck <= 1'b0;
|
|
|
|
update_dr_csff <= 1'b0;
|
|
update_dr_cpu <= 1'b0;
|
|
end
|
|
else
|
|
begin
|
|
busy_csff <= busy_cpu;
|
|
busy_tck <= busy_csff;
|
|
|
|
update_dr_csff <= update_dr_i;
|
|
update_dr_cpu <= update_dr_csff;
|
|
end
|
|
end
|
|
|
|
|
|
// Detecting overrun when write operation.
|
|
always @ (posedge cpu_clk_i or posedge rst_i)
|
|
begin
|
|
if (rst_i)
|
|
cpu_overrun <= 1'b0;
|
|
else if(start_cpu_wr && (!start_cpu_wr_q) && cpu_ack_i)
|
|
cpu_overrun <= 1'b1;
|
|
else if(update_dr_cpu) // error remains active until update_dr arrives
|
|
cpu_overrun <= 1'b0;
|
|
end
|
|
|
|
|
|
// Detecting underrun when read operation
|
|
always @ (posedge tck_i or posedge rst_i)
|
|
begin
|
|
if (rst_i)
|
|
underrun_tck <= 1'b0;
|
|
else if(latch_data && (!fifo_full) && (!data_cnt_end))
|
|
underrun_tck <= 1'b1;
|
|
else if(update_dr_i) // error remains active until update_dr arrives
|
|
underrun_tck <= 1'b0;
|
|
end
|
|
|
|
|
|
always @ (posedge tck_i or posedge rst_i)
|
|
begin
|
|
if (rst_i)
|
|
begin
|
|
cpu_overrun_csff <= 1'b0;
|
|
cpu_overrun_tck <= 1'b0;
|
|
|
|
cpu_ack_csff <= 1'b0;
|
|
cpu_ack_tck <= 1'b0;
|
|
end
|
|
else
|
|
begin
|
|
cpu_overrun_csff <= cpu_overrun;
|
|
cpu_overrun_tck <= cpu_overrun_csff;
|
|
|
|
cpu_ack_csff <= cpu_ack_i;
|
|
cpu_ack_tck <= cpu_ack_csff;
|
|
end
|
|
end
|
|
|
|
|
|
|
|
always @ (posedge cpu_clk_i or posedge rst_i)
|
|
begin
|
|
if (rst_i)
|
|
begin
|
|
cpu_ce_csff <= 1'b0;
|
|
mem_ptr_init <= 1'b0;
|
|
end
|
|
else
|
|
begin
|
|
cpu_ce_csff <= cpu_ce_i;
|
|
mem_ptr_init <= ~cpu_ce_csff;
|
|
end
|
|
end
|
|
|
|
|
|
// Logic for latching data that is read from cpu
|
|
always @ (posedge cpu_clk_i)
|
|
begin
|
|
if (cpu_ack_i && (!cpu_ack_q))
|
|
begin
|
|
mem[0] <= cpu_data_i[31:24];
|
|
mem[1] <= cpu_data_i[23:16];
|
|
mem[2] <= cpu_data_i[15:08];
|
|
mem[3] <= cpu_data_i[07:00];
|
|
end
|
|
end
|
|
|
|
|
|
assign input_data = {mem[0], mem[1], mem[2], mem[3]};
|
|
|
|
|
|
// Fifo counter and empty/full detection
|
|
always @ (posedge tck_i or posedge rst_i)
|
|
begin
|
|
if (rst_i)
|
|
fifo_full <= 1'h0;
|
|
else if (update_dr_i)
|
|
fifo_full <= 1'h0;
|
|
else if (cpu_end_tck && (!cpu_end_tck_q) && (!latch_data) && (!fifo_full)) // incrementing
|
|
fifo_full <= 1'b1;
|
|
else if (!(cpu_end_tck && (!cpu_end_tck_q)) && latch_data && (fifo_full)) // decrementing
|
|
fifo_full <= 1'h0;
|
|
end
|
|
|
|
|
|
|
|
// TDO multiplexer
|
|
always @ (pause_dr_i or busy_tck or crc_cnt_end or crc_cnt_end_q or curr_cmd_wr_comm or curr_cmd_wr_ctrl or curr_cmd_go or acc_type_write or acc_type_read or crc_match_i or data_cnt_end or dr or data_cnt_end_q or crc_match_reg or status_cnt_en or status or addr_len_cnt_end or addr_len_cnt_end_q or curr_cmd_rd_comm or curr_cmd_rd_ctrl)
|
|
begin
|
|
if (pause_dr_i)
|
|
begin
|
|
tdo_o = busy_tck;
|
|
end
|
|
else if (crc_cnt_end && (!crc_cnt_end_q) && (curr_cmd_wr_comm || curr_cmd_wr_ctrl || curr_cmd_go && acc_type_write ))
|
|
begin
|
|
tdo_o = ~crc_match_i;
|
|
end
|
|
else if (curr_cmd_go && acc_type_read && crc_cnt_end && (!data_cnt_end))
|
|
begin
|
|
tdo_o = dr[31];
|
|
end
|
|
else if (curr_cmd_go && acc_type_read && data_cnt_end && (!data_cnt_end_q))
|
|
begin
|
|
tdo_o = ~crc_match_reg;
|
|
end
|
|
else if ((curr_cmd_rd_comm || curr_cmd_rd_ctrl) && addr_len_cnt_end && (!addr_len_cnt_end_q))
|
|
begin
|
|
tdo_o = ~crc_match_reg;
|
|
end
|
|
else if ((curr_cmd_rd_comm || curr_cmd_rd_ctrl) && crc_cnt_end && (!addr_len_cnt_end))
|
|
begin
|
|
tdo_o = dr[`DBG_CPU_ACC_TYPE_LEN + `DBG_CPU_ADR_LEN + `DBG_CPU_LEN_LEN -1];
|
|
end
|
|
else if (status_cnt_en)
|
|
begin
|
|
tdo_o = status[3];
|
|
end
|
|
else
|
|
begin
|
|
tdo_o = 1'b0;
|
|
end
|
|
end
|
|
|
|
|
|
// Status register
|
|
always @ (posedge tck_i or posedge rst_i)
|
|
begin
|
|
if (rst_i)
|
|
begin
|
|
status <= {`DBG_CPU_STATUS_LEN{1'b0}};
|
|
end
|
|
else if(crc_cnt_end && (!crc_cnt_end_q) && (!(curr_cmd_go && acc_type_read)))
|
|
begin
|
|
status <= {1'b0, 1'b0, cpu_overrun_tck, crc_match_i};
|
|
end
|
|
else if (data_cnt_end && (!data_cnt_end_q) && curr_cmd_go && acc_type_read)
|
|
begin
|
|
status <= {1'b0, 1'b0, underrun_tck, crc_match_reg};
|
|
end
|
|
else if (addr_len_cnt_end && (!addr_len_cnt_end) && (curr_cmd_rd_comm || curr_cmd_rd_ctrl))
|
|
begin
|
|
status <= {1'b0, 1'b0, 1'b0, crc_match_reg};
|
|
end
|
|
else if (shift_dr_i && (!status_cnt_end))
|
|
begin
|
|
status <= {status[`DBG_CPU_STATUS_LEN -2:0], status[`DBG_CPU_STATUS_LEN -1]};
|
|
end
|
|
end
|
|
// Following status is shifted out (MSB first):
|
|
// 3. bit: 1 if crc is OK, else 0
|
|
// 2. bit: 1'b0
|
|
// 1. bit: 0
|
|
// 0. bit: 1 if overrun occured during write (data couldn't be written fast enough)
|
|
// or underrun occured during read (data couldn't be read fast enough)
|
|
|
|
|
|
|
|
// Connecting cpu registers
|
|
assign cpu_reg_we = crc_cnt_end && (!crc_cnt_end_q) && crc_match_i && curr_cmd_wr_ctrl;
|
|
assign cpu_reg_data_i = dr[`DBG_CPU_DR_LEN -1:`DBG_CPU_DR_LEN -`DBG_CPU_CTRL_LEN];
|
|
|
|
dbg_cpu_registers i_dbg_cpu_registers
|
|
(
|
|
.data_i (cpu_reg_data_i),
|
|
.we_i (cpu_reg_we),
|
|
.tck_i (tck_i),
|
|
.bp_i (cpu_bp_i),
|
|
.rst_i (rst_i),
|
|
.cpu_clk_i (cpu_clk_i),
|
|
.ctrl_reg_o (ctrl_reg),
|
|
.cpu_stall_o (cpu_reg_stall),
|
|
.cpu_rst_o (cpu_rst_o)
|
|
);
|
|
|
|
|
|
|
|
|
|
|
|
endmodule
|
|
|
|
|
No newline at end of file
|
No newline at end of file
|
