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Line 37... |
//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: dbg_cpu.v,v $
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// Revision 1.12 2004/04/08 14:15:10 igorm
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// CTRL READ fixed. Stall bit was not shifted out OK. Error appeared in last
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// check-in.
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//
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// Revision 1.11 2004/04/07 19:28:55 igorm
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// Zero is shifted out when CTRL_READ command is active.
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//
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// Revision 1.10 2004/04/01 10:22:45 igorm
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// Signals for easier debugging removed.
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//
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// Revision 1.9 2004/03/31 14:34:09 igorm
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// data_cnt_lim length changed to reduce number of warnings.
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//
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// Revision 1.8 2004/03/28 20:27:01 igorm
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// New release of the debug interface (3rd. release).
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//
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// Revision 1.7 2004/01/25 14:04:18 mohor
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// All flipflops are reset.
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//
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// Revision 1.6 2004/01/22 13:58:53 mohor
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// Port signals are all set to zero after reset.
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//
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// Revision 1.5 2004/01/19 07:32:41 simons
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// Reset values width added because of FV, a good sentence changed because some tools can not handle it.
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//
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// Revision 1.4 2004/01/17 18:38:11 mohor
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// cpu_tall_o is set with cpu_stb_o or register.
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//
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// Revision 1.3 2004/01/17 18:01:24 mohor
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// New version.
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//
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// Revision 1.2 2004/01/17 17:01:14 mohor
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// Almost finished.
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//
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// Revision 1.1 2004/01/16 14:53:31 mohor
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// *** empty log message ***
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//
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//
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//
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// synopsys translate_off
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// synopsys translate_off
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`include "timescale.v"
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`include "timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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`include "dbg_cpu_defines.v"
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`include "dbg_cpu_defines.v"
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| Line 284... |
Line 241... |
begin
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begin
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dr[31:0] <= {dr[30:0], 1'b0};
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dr[31:0] <= {dr[30:0], 1'b0};
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latch_data <= 1'b0;
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latch_data <= 1'b0;
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end
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end
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end
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end
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default: begin
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end
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endcase
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endcase
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end
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end
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else if (enable && (!addr_len_cnt_end))
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else if (enable && (!addr_len_cnt_end))
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begin
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begin
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dr <= {dr[`DBG_CPU_DR_LEN -2:0], tdi_i};
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dr <= {dr[`DBG_CPU_DR_LEN -2:0], tdi_i};
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| Line 305... |
Line 265... |
if (rst_i)
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if (rst_i)
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cmd_cnt <= {`DBG_CPU_CMD_CNT_WIDTH{1'b0}};
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cmd_cnt <= {`DBG_CPU_CMD_CNT_WIDTH{1'b0}};
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else if (update_dr_i)
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else if (update_dr_i)
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cmd_cnt <= {`DBG_CPU_CMD_CNT_WIDTH{1'b0}};
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cmd_cnt <= {`DBG_CPU_CMD_CNT_WIDTH{1'b0}};
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else if (cmd_cnt_en)
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else if (cmd_cnt_en)
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cmd_cnt <= cmd_cnt + 1'b1;
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cmd_cnt <= cmd_cnt + 1;
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end
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end
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// Assigning current command
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// Assigning current command
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always @ (posedge tck_i or posedge rst_i)
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always @ (posedge tck_i or posedge rst_i)
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| Line 355... |
Line 315... |
if (rst_i)
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if (rst_i)
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addr_len_cnt <= 6'h0;
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addr_len_cnt <= 6'h0;
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else if (update_dr_i)
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else if (update_dr_i)
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addr_len_cnt <= 6'h0;
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addr_len_cnt <= 6'h0;
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else if (addr_len_cnt_en)
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else if (addr_len_cnt_en)
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addr_len_cnt <= addr_len_cnt + 1'b1;
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addr_len_cnt <= addr_len_cnt + 1;
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end
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end
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always @ (enable or data_cnt_end or cmd_cnt_end or curr_cmd_go or acc_type_write or acc_type_read or crc_cnt_end)
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always @ (enable or data_cnt_end or cmd_cnt_end or curr_cmd_go or acc_type_write or acc_type_read or crc_cnt_end)
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begin
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begin
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| Line 379... |
Line 339... |
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// Data counter
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// Data counter
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always @ (posedge tck_i or posedge rst_i)
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always @ (posedge tck_i or posedge rst_i)
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begin
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begin
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if (rst_i)
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if (rst_i)
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data_cnt <= {`DBG_CPU_DATA_CNT_WIDTH{1'b0}};
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data_cnt <= {`DBG_CPU_DATA_CNT_WIDTH+1{1'b0}};
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else if (update_dr_i)
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else if (update_dr_i)
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data_cnt <= {`DBG_CPU_DATA_CNT_WIDTH{1'b0}};
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data_cnt <= {`DBG_CPU_DATA_CNT_WIDTH+1{1'b0}};
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else if (data_cnt_en)
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else if (data_cnt_en)
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data_cnt <= data_cnt + 1'b1;
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data_cnt <= data_cnt + 1;
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end
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end
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// Upper limit. Data counter counts until this value is reached.
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// Upper limit. Data counter counts until this value is reached.
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always @ (posedge tck_i or posedge rst_i)
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always @ (posedge tck_i or posedge rst_i)
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begin
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begin
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if (rst_i)
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if (rst_i)
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data_cnt_limit <= {`DBG_CPU_DATA_CNT_LIM_WIDTH{1'b0}};
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data_cnt_limit <= {`DBG_CPU_DATA_CNT_LIM_WIDTH+1{1'b0}};
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else if (update_dr_i)
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else if (update_dr_i)
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data_cnt_limit <= len + 1'b1;
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data_cnt_limit <= len + 1;
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end
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end
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always @ (enable or crc_cnt_end or curr_cmd_rd_comm or curr_cmd_rd_ctrl or curr_cmd_wr_comm or curr_cmd_wr_ctrl or curr_cmd_go or addr_len_cnt_end or data_cnt_end or acc_type_write or acc_type_read or cmd_cnt_end)
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always @ (enable or crc_cnt_end or curr_cmd_rd_comm or curr_cmd_rd_ctrl or curr_cmd_wr_comm or curr_cmd_wr_ctrl or curr_cmd_go or addr_len_cnt_end or data_cnt_end or acc_type_write or acc_type_read or cmd_cnt_end)
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begin
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begin
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| Line 422... |
Line 382... |
always @ (posedge tck_i or posedge rst_i)
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always @ (posedge tck_i or posedge rst_i)
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begin
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begin
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if (rst_i)
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if (rst_i)
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crc_cnt <= {`DBG_CPU_CRC_CNT_WIDTH{1'b0}};
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crc_cnt <= {`DBG_CPU_CRC_CNT_WIDTH{1'b0}};
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else if(crc_cnt_en)
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else if(crc_cnt_en)
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crc_cnt <= crc_cnt + 1'b1;
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crc_cnt <= crc_cnt + 1;
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else if (update_dr_i)
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else if (update_dr_i)
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crc_cnt <= {`DBG_CPU_CRC_CNT_WIDTH{1'b0}};
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crc_cnt <= {`DBG_CPU_CRC_CNT_WIDTH{1'b0}};
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end
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end
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assign cmd_cnt_end = cmd_cnt == `DBG_CPU_CMD_LEN;
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assign cmd_cnt_end = cmd_cnt == `DBG_CPU_CMD_LEN;
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| Line 460... |
Line 420... |
if (rst_i)
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if (rst_i)
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status_cnt <= {`DBG_CPU_STATUS_CNT_WIDTH{1'b0}};
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status_cnt <= {`DBG_CPU_STATUS_CNT_WIDTH{1'b0}};
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else if (update_dr_i)
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else if (update_dr_i)
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status_cnt <= {`DBG_CPU_STATUS_CNT_WIDTH{1'b0}};
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status_cnt <= {`DBG_CPU_STATUS_CNT_WIDTH{1'b0}};
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else if (status_cnt_en)
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else if (status_cnt_en)
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status_cnt <= status_cnt + 1'b1;
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status_cnt <= status_cnt + 1;
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end
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end
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always @ (enable or status_cnt_end or crc_cnt_end or curr_cmd_rd_comm or curr_cmd_rd_ctrl or
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always @ (enable or status_cnt_end or crc_cnt_end or curr_cmd_rd_comm or curr_cmd_rd_ctrl or
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curr_cmd_wr_comm or curr_cmd_wr_ctrl or curr_cmd_go or acc_type_write or
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curr_cmd_wr_comm or curr_cmd_wr_ctrl or curr_cmd_go or acc_type_write or
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| Line 530... |
Line 490... |
always @ (posedge tck_i or posedge rst_i)
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always @ (posedge tck_i or posedge rst_i)
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begin
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begin
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if (rst_i)
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if (rst_i)
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len_var <= {1'b0, {`DBG_CPU_LEN_LEN{1'b0}}};
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len_var <= {1'b0, {`DBG_CPU_LEN_LEN{1'b0}}};
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else if(update_dr_i)
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else if(update_dr_i)
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len_var <= len + 1'b1;
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len_var <= len + 'd1;
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else if (start_rd_tck)
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else if (start_rd_tck)
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begin
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begin
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if (len_var > 'd4)
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if (len_var > 4)
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len_var <= len_var - 3'd4;
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len_var <= len_var - 'd4;
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else
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else
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len_var <= {1'b0, {`DBG_CPU_LEN_LEN{1'b0}}};
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len_var <= {1'b0, {`DBG_CPU_LEN_LEN{1'b0}}};
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end
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end
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end
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end
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| Line 569... |
Line 529... |
always @ (posedge tck_i or posedge rst_i)
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always @ (posedge tck_i or posedge rst_i)
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begin
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begin
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if (rst_i)
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if (rst_i)
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begin
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begin
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start_wr_tck <= 1'b0;
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start_wr_tck <= 1'b0;
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cpu_dat_tmp <= 32'h0;
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cpu_dat_tmp <= 32'd0;
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end
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end
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else if (curr_cmd_go && acc_type_write)
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else if (curr_cmd_go && acc_type_write)
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begin
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begin
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if (long_q)
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if (long_q)
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begin
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begin
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| Line 684... |
Line 644... |
cpu_addr_dsff <= 32'h0;
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cpu_addr_dsff <= 32'h0;
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else if (set_addr_cpu && (!set_addr_cpu_q)) // Setting starting address
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else if (set_addr_cpu && (!set_addr_cpu_q)) // Setting starting address
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cpu_addr_dsff <= adr;
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cpu_addr_dsff <= adr;
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else if (cpu_ack_i && (!cpu_ack_q))
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else if (cpu_ack_i && (!cpu_ack_q))
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//cpu_addr_dsff <= cpu_addr_dsff + 3'd4;
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//cpu_addr_dsff <= cpu_addr_dsff + 3'd4;
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cpu_addr_dsff <= cpu_addr_dsff + 3'd1; // Increment by just 1, to allow block reading -- jb 090901
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// Increment by just 1, to allow block reading -- jb 090901
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cpu_addr_dsff <= cpu_addr_dsff + 'd1;
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end
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end
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assign cpu_addr_o = cpu_addr_dsff;
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assign cpu_addr_o = cpu_addr_dsff;
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