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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [dbg_if/] [dbg_cpu.v] - Diff between revs 360 and 363

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Rev 360 Rev 363
Line 37... Line 37...
//// You should have received a copy of the GNU Lesser General    ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
 
// CVS Revision History
 
//
 
// $Log: dbg_cpu.v,v $
 
// Revision 1.12  2004/04/08 14:15:10  igorm
 
// CTRL READ fixed. Stall bit was not shifted out OK. Error appeared in last
 
// check-in.
 
//
 
// Revision 1.11  2004/04/07 19:28:55  igorm
 
// Zero is shifted out when CTRL_READ command is active.
 
//
 
// Revision 1.10  2004/04/01 10:22:45  igorm
 
// Signals for easier debugging removed.
 
//
 
// Revision 1.9  2004/03/31 14:34:09  igorm
 
// data_cnt_lim length changed to reduce number of warnings.
 
//
 
// Revision 1.8  2004/03/28 20:27:01  igorm
 
// New release of the debug interface (3rd. release).
 
//
 
// Revision 1.7  2004/01/25 14:04:18  mohor
 
// All flipflops are reset.
 
//
 
// Revision 1.6  2004/01/22 13:58:53  mohor
 
// Port signals are all set to zero after reset.
 
//
 
// Revision 1.5  2004/01/19 07:32:41  simons
 
// Reset values width added because of FV, a good sentence changed because some tools can not handle it.
 
//
 
// Revision 1.4  2004/01/17 18:38:11  mohor
 
// cpu_tall_o is set with cpu_stb_o or register.
 
//
 
// Revision 1.3  2004/01/17 18:01:24  mohor
 
// New version.
 
//
 
// Revision 1.2  2004/01/17 17:01:14  mohor
 
// Almost finished.
 
//
 
// Revision 1.1  2004/01/16 14:53:31  mohor
 
// *** empty log message ***
 
//
 
//
 
//
 
 
 
// synopsys translate_off
// synopsys translate_off
`include "timescale.v"
`include "timescale.v"
// synopsys translate_on
// synopsys translate_on
`include "dbg_cpu_defines.v"
`include "dbg_cpu_defines.v"
Line 284... Line 241...
                        begin
                        begin
                          dr[31:0] <=  {dr[30:0], 1'b0};
                          dr[31:0] <=  {dr[30:0], 1'b0};
                          latch_data <=  1'b0;
                          latch_data <=  1'b0;
                        end
                        end
                    end
                    end
 
        default: begin
 
 
 
        end
      endcase
      endcase
    end
    end
  else if (enable && (!addr_len_cnt_end))
  else if (enable && (!addr_len_cnt_end))
    begin
    begin
      dr <=  {dr[`DBG_CPU_DR_LEN -2:0], tdi_i};
      dr <=  {dr[`DBG_CPU_DR_LEN -2:0], tdi_i};
Line 305... Line 265...
  if (rst_i)
  if (rst_i)
    cmd_cnt <=  {`DBG_CPU_CMD_CNT_WIDTH{1'b0}};
    cmd_cnt <=  {`DBG_CPU_CMD_CNT_WIDTH{1'b0}};
  else if (update_dr_i)
  else if (update_dr_i)
    cmd_cnt <=  {`DBG_CPU_CMD_CNT_WIDTH{1'b0}};
    cmd_cnt <=  {`DBG_CPU_CMD_CNT_WIDTH{1'b0}};
  else if (cmd_cnt_en)
  else if (cmd_cnt_en)
    cmd_cnt <=  cmd_cnt + 1'b1;
    cmd_cnt <=  cmd_cnt + 1;
end
end
 
 
 
 
// Assigning current command
// Assigning current command
always @ (posedge tck_i or posedge rst_i)
always @ (posedge tck_i or posedge rst_i)
Line 355... Line 315...
  if (rst_i)
  if (rst_i)
    addr_len_cnt <=  6'h0;
    addr_len_cnt <=  6'h0;
  else if (update_dr_i)
  else if (update_dr_i)
    addr_len_cnt <=  6'h0;
    addr_len_cnt <=  6'h0;
  else if (addr_len_cnt_en)
  else if (addr_len_cnt_en)
    addr_len_cnt <=  addr_len_cnt + 1'b1;
    addr_len_cnt <=  addr_len_cnt + 1;
end
end
 
 
 
 
always @ (enable or data_cnt_end or cmd_cnt_end or curr_cmd_go or acc_type_write or acc_type_read or crc_cnt_end)
always @ (enable or data_cnt_end or cmd_cnt_end or curr_cmd_go or acc_type_write or acc_type_read or crc_cnt_end)
begin
begin
Line 379... Line 339...
 
 
// Data counter
// Data counter
always @ (posedge tck_i or posedge rst_i)
always @ (posedge tck_i or posedge rst_i)
begin
begin
  if (rst_i)
  if (rst_i)
    data_cnt <=  {`DBG_CPU_DATA_CNT_WIDTH{1'b0}};
    data_cnt <=  {`DBG_CPU_DATA_CNT_WIDTH+1{1'b0}};
  else if (update_dr_i)
  else if (update_dr_i)
    data_cnt <=  {`DBG_CPU_DATA_CNT_WIDTH{1'b0}};
    data_cnt <=  {`DBG_CPU_DATA_CNT_WIDTH+1{1'b0}};
  else if (data_cnt_en)
  else if (data_cnt_en)
    data_cnt <=  data_cnt + 1'b1;
    data_cnt <=  data_cnt + 1;
end
end
 
 
 
 
 
 
// Upper limit. Data counter counts until this value is reached.
// Upper limit. Data counter counts until this value is reached.
always @ (posedge tck_i or posedge rst_i)
always @ (posedge tck_i or posedge rst_i)
begin
begin
  if (rst_i)
  if (rst_i)
    data_cnt_limit <=  {`DBG_CPU_DATA_CNT_LIM_WIDTH{1'b0}};
    data_cnt_limit <=  {`DBG_CPU_DATA_CNT_LIM_WIDTH+1{1'b0}};
  else if (update_dr_i)
  else if (update_dr_i)
    data_cnt_limit <=  len + 1'b1;
    data_cnt_limit <=  len + 1;
end
end
 
 
 
 
always @ (enable or crc_cnt_end or curr_cmd_rd_comm or curr_cmd_rd_ctrl or curr_cmd_wr_comm or curr_cmd_wr_ctrl or curr_cmd_go or addr_len_cnt_end or data_cnt_end or acc_type_write or acc_type_read or cmd_cnt_end)
always @ (enable or crc_cnt_end or curr_cmd_rd_comm or curr_cmd_rd_ctrl or curr_cmd_wr_comm or curr_cmd_wr_ctrl or curr_cmd_go or addr_len_cnt_end or data_cnt_end or acc_type_write or acc_type_read or cmd_cnt_end)
begin
begin
Line 422... Line 382...
always @ (posedge tck_i or posedge rst_i)
always @ (posedge tck_i or posedge rst_i)
begin
begin
  if (rst_i)
  if (rst_i)
    crc_cnt <=  {`DBG_CPU_CRC_CNT_WIDTH{1'b0}};
    crc_cnt <=  {`DBG_CPU_CRC_CNT_WIDTH{1'b0}};
  else if(crc_cnt_en)
  else if(crc_cnt_en)
    crc_cnt <=  crc_cnt + 1'b1;
    crc_cnt <=  crc_cnt + 1;
  else if (update_dr_i)
  else if (update_dr_i)
    crc_cnt <=  {`DBG_CPU_CRC_CNT_WIDTH{1'b0}};
    crc_cnt <=  {`DBG_CPU_CRC_CNT_WIDTH{1'b0}};
end
end
 
 
assign cmd_cnt_end      = cmd_cnt      == `DBG_CPU_CMD_LEN;
assign cmd_cnt_end      = cmd_cnt      == `DBG_CPU_CMD_LEN;
Line 460... Line 420...
  if (rst_i)
  if (rst_i)
    status_cnt <=  {`DBG_CPU_STATUS_CNT_WIDTH{1'b0}};
    status_cnt <=  {`DBG_CPU_STATUS_CNT_WIDTH{1'b0}};
  else if (update_dr_i)
  else if (update_dr_i)
    status_cnt <=  {`DBG_CPU_STATUS_CNT_WIDTH{1'b0}};
    status_cnt <=  {`DBG_CPU_STATUS_CNT_WIDTH{1'b0}};
  else if (status_cnt_en)
  else if (status_cnt_en)
    status_cnt <=  status_cnt + 1'b1;
    status_cnt <=  status_cnt + 1;
end
end
 
 
 
 
always @ (enable or status_cnt_end or crc_cnt_end or curr_cmd_rd_comm or curr_cmd_rd_ctrl or
always @ (enable or status_cnt_end or crc_cnt_end or curr_cmd_rd_comm or curr_cmd_rd_ctrl or
          curr_cmd_wr_comm or curr_cmd_wr_ctrl or curr_cmd_go or acc_type_write or
          curr_cmd_wr_comm or curr_cmd_wr_ctrl or curr_cmd_go or acc_type_write or
Line 530... Line 490...
always @ (posedge tck_i or posedge rst_i)
always @ (posedge tck_i or posedge rst_i)
begin
begin
  if (rst_i)
  if (rst_i)
    len_var <=  {1'b0, {`DBG_CPU_LEN_LEN{1'b0}}};
    len_var <=  {1'b0, {`DBG_CPU_LEN_LEN{1'b0}}};
  else if(update_dr_i)
  else if(update_dr_i)
    len_var <=  len + 1'b1;
    len_var <=  len + 'd1;
  else if (start_rd_tck)
  else if (start_rd_tck)
    begin
    begin
      if (len_var > 'd4)
      if (len_var > 4)
        len_var <=  len_var - 3'd4;
        len_var <=  len_var - 'd4;
      else
      else
        len_var <=  {1'b0, {`DBG_CPU_LEN_LEN{1'b0}}};
        len_var <=  {1'b0, {`DBG_CPU_LEN_LEN{1'b0}}};
    end
    end
end
end
 
 
Line 569... Line 529...
always @ (posedge tck_i or posedge rst_i)
always @ (posedge tck_i or posedge rst_i)
begin
begin
  if (rst_i)
  if (rst_i)
    begin
    begin
      start_wr_tck <=  1'b0;
      start_wr_tck <=  1'b0;
      cpu_dat_tmp <=  32'h0;
      cpu_dat_tmp <=  32'd0;
    end
    end
  else if (curr_cmd_go && acc_type_write)
  else if (curr_cmd_go && acc_type_write)
    begin
    begin
      if (long_q)
      if (long_q)
        begin
        begin
Line 684... Line 644...
    cpu_addr_dsff <=  32'h0;
    cpu_addr_dsff <=  32'h0;
  else if (set_addr_cpu && (!set_addr_cpu_q)) // Setting starting address
  else if (set_addr_cpu && (!set_addr_cpu_q)) // Setting starting address
    cpu_addr_dsff <=  adr;
    cpu_addr_dsff <=  adr;
  else if (cpu_ack_i && (!cpu_ack_q))
  else if (cpu_ack_i && (!cpu_ack_q))
    //cpu_addr_dsff <=  cpu_addr_dsff + 3'd4;
    //cpu_addr_dsff <=  cpu_addr_dsff + 3'd4;
    cpu_addr_dsff <=  cpu_addr_dsff + 3'd1; // Increment by just 1, to allow block reading -- jb 090901
    // Increment by just 1, to allow block reading -- jb 090901
 
    cpu_addr_dsff <=  cpu_addr_dsff + 'd1;
end
end
 
 
 
 
assign cpu_addr_o = cpu_addr_dsff;
assign cpu_addr_o = cpu_addr_dsff;
 
 

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