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//////////////////////////////////////////////////////////////////////
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//// ////
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//// dbg_crc32_d1.v ////
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//// ////
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//// ////
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//// This file is part of the SoC Debug Interface. ////
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//// http://www.opencores.org/projects/DebugInterface/ ////
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//// ////
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//// Author(s): ////
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//// Igor Mohor (igorm@opencores.org) ////
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//// ////
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//// ////
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//// All additional information is avaliable in the README.txt ////
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//// file. ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2000 - 2004 Authors ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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// File: CRC32_D1.v
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// Date: Thu Nov 27 13:56:49 2003
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//
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// Copyright (C) 1999-2003 Easics NV.
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// This source file may be used and distributed without restriction
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// provided that this copyright statement is not removed from the file
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// and that any derivative work contains the original copyright notice
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// and the associated disclaimer.
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//
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// THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY EXPRESS
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// OR IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
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// WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
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//
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// Purpose: Verilog module containing a synthesizable CRC function
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// * polynomial: (0 1 2 4 5 7 8 10 11 12 16 22 23 26 32)
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// * data width: 1
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//
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// Info: janz@easics.be (Jan Zegers)
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// http://www.easics.com
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///////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: dbg_crc32_d1.v,v $
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// Revision 1.3 2004/03/28 20:27:02 igorm
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// New release of the debug interface (3rd. release).
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//
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// Revision 1.2 2003/12/23 15:26:26 mohor
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// Small fix.
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//
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// Revision 1.1 2003/12/23 15:09:04 mohor
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// New directory structure. New version of the debug interface.
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//
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//
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//
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//
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// synopsys translate_off
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`include "timescale.v"
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// synopsys translate_on
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module dbg_crc32_d1 (data, enable, shift, rst, sync_rst, crc_out, clk, crc_match);
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input data;
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input enable;
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input shift;
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input rst;
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input sync_rst;
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input clk;
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output crc_out;
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output crc_match;
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reg [31:0] crc;
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wire [31:0] new_crc;
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assign new_crc[0] = data ^ crc[31];
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assign new_crc[1] = data ^ crc[0] ^ crc[31];
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assign new_crc[2] = data ^ crc[1] ^ crc[31];
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assign new_crc[3] = crc[2];
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assign new_crc[4] = data ^ crc[3] ^ crc[31];
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assign new_crc[5] = data ^ crc[4] ^ crc[31];
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assign new_crc[6] = crc[5];
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assign new_crc[7] = data ^ crc[6] ^ crc[31];
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assign new_crc[8] = data ^ crc[7] ^ crc[31];
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assign new_crc[9] = crc[8];
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assign new_crc[10] = data ^ crc[9] ^ crc[31];
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assign new_crc[11] = data ^ crc[10] ^ crc[31];
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assign new_crc[12] = data ^ crc[11] ^ crc[31];
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assign new_crc[13] = crc[12];
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assign new_crc[14] = crc[13];
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assign new_crc[15] = crc[14];
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assign new_crc[16] = data ^ crc[15] ^ crc[31];
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assign new_crc[17] = crc[16];
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assign new_crc[18] = crc[17];
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assign new_crc[19] = crc[18];
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assign new_crc[20] = crc[19];
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assign new_crc[21] = crc[20];
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assign new_crc[22] = data ^ crc[21] ^ crc[31];
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assign new_crc[23] = data ^ crc[22] ^ crc[31];
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assign new_crc[24] = crc[23];
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assign new_crc[25] = crc[24];
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assign new_crc[26] = data ^ crc[25] ^ crc[31];
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assign new_crc[27] = crc[26];
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assign new_crc[28] = crc[27];
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assign new_crc[29] = crc[28];
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assign new_crc[30] = crc[29];
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assign new_crc[31] = crc[30];
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always @ (posedge clk or posedge rst)
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begin
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if(rst)
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crc[31:0] <= 32'hffffffff;
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else if(sync_rst)
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crc[31:0] <= 32'hffffffff;
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else if(enable)
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crc[31:0] <= new_crc;
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else if (shift)
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crc[31:0] <= {crc[30:0], 1'b0};
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end
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assign crc_match = (crc == 32'h0);
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assign crc_out = crc[31];
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endmodule
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