| Line 394... |
Line 394... |
always @ (posedge tck_i or posedge rst_i)
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always @ (posedge tck_i or posedge rst_i)
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begin
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begin
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if (rst_i)
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if (rst_i)
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data_cnt <= {`DBG_TOP_DATA_CNT{1'b0}};
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data_cnt <= {`DBG_TOP_DATA_CNT{1'b0}};
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else if(shift_dr_i & (~data_cnt_end))
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else if(shift_dr_i & (~data_cnt_end))
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data_cnt <= data_cnt + 1'b1;
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data_cnt <= data_cnt + 1;
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else if (update_dr_i)
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else if (update_dr_i)
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data_cnt <= {`DBG_TOP_DATA_CNT{1'b0}};
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data_cnt <= {`DBG_TOP_DATA_CNT{1'b0}};
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end
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end
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| Line 409... |
Line 409... |
always @ (posedge tck_i or posedge rst_i)
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always @ (posedge tck_i or posedge rst_i)
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begin
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begin
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if (rst_i)
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if (rst_i)
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crc_cnt <= {`DBG_TOP_CRC_CNT{1'b0}};
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crc_cnt <= {`DBG_TOP_CRC_CNT{1'b0}};
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else if(shift_dr_i & data_cnt_end & (~crc_cnt_end) & module_select)
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else if(shift_dr_i & data_cnt_end & (~crc_cnt_end) & module_select)
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crc_cnt <= crc_cnt + 1'b1;
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crc_cnt <= crc_cnt + 1;
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else if (update_dr_i)
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else if (update_dr_i)
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crc_cnt <= {`DBG_TOP_CRC_CNT{1'b0}};
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crc_cnt <= {`DBG_TOP_CRC_CNT{1'b0}};
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end
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end
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assign crc_cnt_end = crc_cnt == `DBG_TOP_CRC_LEN;
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assign crc_cnt_end = crc_cnt == `DBG_TOP_CRC_LEN;
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| Line 432... |
Line 432... |
always @ (posedge tck_i or posedge rst_i)
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always @ (posedge tck_i or posedge rst_i)
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begin
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begin
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if (rst_i)
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if (rst_i)
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status_cnt <= {`DBG_TOP_STATUS_CNT_WIDTH{1'b0}};
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status_cnt <= {`DBG_TOP_STATUS_CNT_WIDTH{1'b0}};
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else if(shift_dr_i & crc_cnt_end & (~status_cnt_end))
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else if(shift_dr_i & crc_cnt_end & (~status_cnt_end))
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status_cnt <= status_cnt + 1'b1;
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status_cnt <= status_cnt + 1;
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else if (update_dr_i)
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else if (update_dr_i)
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status_cnt <= {`DBG_TOP_STATUS_CNT_WIDTH{1'b0}};
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status_cnt <= {`DBG_TOP_STATUS_CNT_WIDTH{1'b0}};
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end
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end
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assign status_cnt_end = status_cnt == `DBG_TOP_STATUS_LEN;
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assign status_cnt_end = status_cnt == `DBG_TOP_STATUS_LEN;
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| Line 500... |
Line 500... |
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always @ (posedge tck_i or posedge rst_i)
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always @ (posedge tck_i or posedge rst_i)
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begin
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begin
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if (rst_i)
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if (rst_i)
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module_dr <= `DBG_TOP_MODULE_DATA_LEN'h0;
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module_dr <= 0;
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else if (data_shift_en)
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else if (data_shift_en)
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module_dr[`DBG_TOP_MODULE_DATA_LEN -1:0] <= {module_dr[`DBG_TOP_MODULE_DATA_LEN -2:0], tdi_i};
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module_dr[`DBG_TOP_MODULE_DATA_LEN -1:0] <= {module_dr[`DBG_TOP_MODULE_DATA_LEN -2:0], tdi_i};
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end
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end
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