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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [dbg_if/] [dbg_if.v] - Diff between revs 360 and 363

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Rev 360 Rev 363
Line 394... Line 394...
always @ (posedge tck_i or posedge rst_i)
always @ (posedge tck_i or posedge rst_i)
begin
begin
  if (rst_i)
  if (rst_i)
    data_cnt <=  {`DBG_TOP_DATA_CNT{1'b0}};
    data_cnt <=  {`DBG_TOP_DATA_CNT{1'b0}};
  else if(shift_dr_i & (~data_cnt_end))
  else if(shift_dr_i & (~data_cnt_end))
    data_cnt <=  data_cnt + 1'b1;
    data_cnt <=  data_cnt + 1;
  else if (update_dr_i)
  else if (update_dr_i)
    data_cnt <=  {`DBG_TOP_DATA_CNT{1'b0}};
    data_cnt <=  {`DBG_TOP_DATA_CNT{1'b0}};
end
end
 
 
 
 
Line 409... Line 409...
always @ (posedge tck_i or posedge rst_i)
always @ (posedge tck_i or posedge rst_i)
begin
begin
  if (rst_i)
  if (rst_i)
    crc_cnt <=  {`DBG_TOP_CRC_CNT{1'b0}};
    crc_cnt <=  {`DBG_TOP_CRC_CNT{1'b0}};
  else if(shift_dr_i & data_cnt_end & (~crc_cnt_end) & module_select)
  else if(shift_dr_i & data_cnt_end & (~crc_cnt_end) & module_select)
    crc_cnt <=  crc_cnt + 1'b1;
    crc_cnt <=  crc_cnt + 1;
  else if (update_dr_i)
  else if (update_dr_i)
    crc_cnt <=  {`DBG_TOP_CRC_CNT{1'b0}};
    crc_cnt <=  {`DBG_TOP_CRC_CNT{1'b0}};
end
end
 
 
assign crc_cnt_end = crc_cnt == `DBG_TOP_CRC_LEN;
assign crc_cnt_end = crc_cnt == `DBG_TOP_CRC_LEN;
Line 432... Line 432...
always @ (posedge tck_i or posedge rst_i)
always @ (posedge tck_i or posedge rst_i)
begin
begin
  if (rst_i)
  if (rst_i)
    status_cnt <=  {`DBG_TOP_STATUS_CNT_WIDTH{1'b0}};
    status_cnt <=  {`DBG_TOP_STATUS_CNT_WIDTH{1'b0}};
  else if(shift_dr_i & crc_cnt_end & (~status_cnt_end))
  else if(shift_dr_i & crc_cnt_end & (~status_cnt_end))
    status_cnt <=  status_cnt + 1'b1;
    status_cnt <=  status_cnt + 1;
  else if (update_dr_i)
  else if (update_dr_i)
    status_cnt <=  {`DBG_TOP_STATUS_CNT_WIDTH{1'b0}};
    status_cnt <=  {`DBG_TOP_STATUS_CNT_WIDTH{1'b0}};
end
end
 
 
assign status_cnt_end = status_cnt == `DBG_TOP_STATUS_LEN;
assign status_cnt_end = status_cnt == `DBG_TOP_STATUS_LEN;
Line 500... Line 500...
 
 
 
 
always @ (posedge tck_i or posedge rst_i)
always @ (posedge tck_i or posedge rst_i)
begin
begin
  if (rst_i)
  if (rst_i)
    module_dr <=  `DBG_TOP_MODULE_DATA_LEN'h0;
    module_dr <=  0;
  else if (data_shift_en)
  else if (data_shift_en)
    module_dr[`DBG_TOP_MODULE_DATA_LEN -1:0] <=  {module_dr[`DBG_TOP_MODULE_DATA_LEN -2:0], tdi_i};
    module_dr[`DBG_TOP_MODULE_DATA_LEN -1:0] <=  {module_dr[`DBG_TOP_MODULE_DATA_LEN -2:0], tdi_i};
end
end
 
 
 
 

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