| Line 239... |
Line 239... |
end
|
end
|
else if (curr_cmd_rd_comm && crc_cnt_31) // Latching data (from iternal regs)
|
else if (curr_cmd_rd_comm && crc_cnt_31) // Latching data (from iternal regs)
|
begin
|
begin
|
dr[`DBG_WB_ACC_TYPE_LEN + `DBG_WB_ADR_LEN + `DBG_WB_LEN_LEN -1:0] <= {acc_type, adr, len};
|
dr[`DBG_WB_ACC_TYPE_LEN + `DBG_WB_ADR_LEN + `DBG_WB_LEN_LEN -1:0] <= {acc_type, adr, len};
|
end
|
end
|
else if (acc_type_read && curr_cmd_go && crc_cnt_31) // Latchind first data (from WB)
|
else if (acc_type_read && curr_cmd_go && crc_cnt_31 && !busy_tck) // Latchind first data (from WB)
|
begin
|
begin
|
dr[31:0] <= input_data[31:0];
|
dr[31:0] <= input_data[31:0];
|
latch_data <= 1'b1;
|
latch_data <= 1'b1;
|
end
|
end
|
else if (acc_type_read && curr_cmd_go && crc_cnt_end) // Latching data (from WB)
|
else if (acc_type_read && curr_cmd_go && crc_cnt_end && !busy_tck && wb_end_tck_q)
|
|
begin
|
|
// Had to wait for data from WB.
|
|
dr[31:0] <= input_data[31:0];
|
|
latch_data <= 1'b1;
|
|
end
|
|
else if (acc_type_read && curr_cmd_go && crc_cnt_end && !busy_tck) // Latching data (from WB)
|
begin
|
begin
|
if (acc_type == `DBG_WB_READ8)
|
if (acc_type == `DBG_WB_READ8)
|
begin
|
begin
|
if(byte & (~byte_q))
|
if(byte & (~byte_q))
|
begin
|
begin
|
| Line 756... |
Line 762... |
|
|
always @ (posedge wb_clk_i or posedge rst_i)
|
always @ (posedge wb_clk_i or posedge rst_i)
|
begin
|
begin
|
if (rst_i)
|
if (rst_i)
|
wb_sel_dsff[3:0] <= 4'h0;
|
wb_sel_dsff[3:0] <= 4'h0;
|
else
|
else if ((start_wb_wr && (!start_wb_wr_q)))
|
begin
|
begin
|
case ({wb_adr_dsff[1:0], acc_type_8bit, acc_type_16bit, acc_type_32bit}) // synthesis parallel_case
|
case ({wb_adr_dsff[1:0], acc_type_8bit, acc_type_16bit, acc_type_32bit}) // synthesis parallel_case
|
{2'd0, 3'b100} : wb_sel_dsff[3:0] <= 4'h8;
|
{2'd0, 3'b100} : wb_sel_dsff[3:0] <= 4'h8;
|
{2'd0, 3'b010} : wb_sel_dsff[3:0] <= 4'hC;
|
{2'd0, 3'b010} : wb_sel_dsff[3:0] <= 4'hC;
|
{2'd0, 3'b001} : wb_sel_dsff[3:0] <= 4'hF;
|
{2'd0, 3'b001} : wb_sel_dsff[3:0] <= 4'hF;
|
| Line 774... |
Line 780... |
end
|
end
|
|
|
|
|
assign wb_sel_o = wb_sel_dsff;
|
assign wb_sel_o = wb_sel_dsff;
|
|
|
|
/*
|
|
always @ (posedge wb_clk_i)
|
|
begin
|
|
wb_we_dsff <= curr_cmd_go && acc_type_write;
|
|
end
|
|
*/
|
|
|
always @ (posedge wb_clk_i)
|
always @ (posedge wb_clk_i or posedge rst_i)
|
begin
|
begin
|
wb_we_dsff <= curr_cmd_go && acc_type_write;
|
if (rst_i)
|
|
wb_we_dsff <= 1'b0;
|
|
else if ((start_wb_wr && (!start_wb_wr_q)))
|
|
wb_we_dsff <= 1'b1;
|
|
else if (wb_ack_i || wb_err_i)
|
|
wb_we_dsff <= 1'b0;
|
end
|
end
|
|
|
|
|
assign wb_we_o = wb_we_dsff;
|
assign wb_we_o = wb_we_dsff;
|
assign wb_cab_o = 1'b0;
|
assign wb_cab_o = 1'b0;
|
| Line 976... |
Line 993... |
4'b0011 : // half
|
4'b0011 : // half
|
begin
|
begin
|
mem[mem_ptr_dsff[1:0]] <= wb_dat_i[15:08];
|
mem[mem_ptr_dsff[1:0]] <= wb_dat_i[15:08];
|
mem[mem_ptr_dsff[1:0]+1'b1] <= wb_dat_i[07:00];
|
mem[mem_ptr_dsff[1:0]+1'b1] <= wb_dat_i[07:00];
|
end
|
end
|
4'b1111 : // long
|
/*4'b1111 : // long*/
|
|
default:
|
begin
|
begin
|
mem[0] <= wb_dat_i[31:24];
|
mem[0] <= wb_dat_i[31:24];
|
mem[1] <= wb_dat_i[23:16];
|
mem[1] <= wb_dat_i[23:16];
|
mem[2] <= wb_dat_i[15:08];
|
mem[2] <= wb_dat_i[15:08];
|
mem[3] <= wb_dat_i[07:00];
|
mem[3] <= wb_dat_i[07:00];
|
end
|
end
|
default : // long
|
/*
|
begin
|
default : // long
|
mem[0] <= 8'hxx;
|
begin
|
mem[1] <= 8'hxx;
|
mem[0] <= 8'hxx;
|
mem[2] <= 8'hxx;
|
mem[1] <= 8'hxx;
|
mem[3] <= 8'hxx;
|
mem[2] <= 8'hxx;
|
end
|
mem[3] <= 8'hxx;
|
|
end
|
|
*/
|
endcase
|
endcase
|
end
|
end
|
end
|
end
|
|
|
|
|
