| Line 37... |
Line 37... |
//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: dbg_wb.v,v $
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// Revision 1.23 2004/04/01 17:21:22 igorm
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// Changes for the FormalPRO.
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//
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// Revision 1.22 2004/04/01 11:56:59 igorm
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// Port names and defines for the supported CPUs changed.
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//
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// Revision 1.21 2004/03/31 14:34:09 igorm
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// data_cnt_lim length changed to reduce number of warnings.
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//
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// Revision 1.20 2004/03/28 20:27:02 igorm
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// New release of the debug interface (3rd. release).
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//
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// Revision 1.19 2004/03/22 16:35:46 igorm
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// Temp version before changing dbg interface.
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//
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// Revision 1.18 2004/01/25 14:04:18 mohor
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// All flipflops are reset.
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//
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// Revision 1.17 2004/01/22 13:58:53 mohor
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// Port signals are all set to zero after reset.
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//
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// Revision 1.16 2004/01/19 07:32:41 simons
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// Reset values width added because of FV, a good sentence changed because some tools can not handle it.
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//
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// Revision 1.15 2004/01/17 18:01:24 mohor
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// New version.
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//
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// Revision 1.14 2004/01/16 14:51:33 mohor
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// cpu registers added.
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//
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// Revision 1.13 2004/01/15 12:09:43 mohor
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// Working.
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//
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// Revision 1.12 2004/01/14 22:59:18 mohor
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// Temp version.
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//
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// Revision 1.11 2004/01/14 12:29:40 mohor
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// temp version. Resets will be changed in next version.
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//
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// Revision 1.10 2004/01/13 11:28:14 mohor
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// tmp version.
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//
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// Revision 1.9 2004/01/10 07:50:24 mohor
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// temp version.
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//
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// Revision 1.8 2004/01/09 12:48:44 mohor
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// tmp version.
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//
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// Revision 1.7 2004/01/08 17:53:36 mohor
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// tmp version.
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//
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// Revision 1.6 2004/01/07 11:58:56 mohor
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// temp4 version.
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//
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// Revision 1.5 2004/01/06 17:15:19 mohor
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// temp3 version.
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//
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// Revision 1.4 2004/01/05 12:16:00 mohor
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// tmp2 version.
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//
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// Revision 1.3 2003/12/23 16:22:46 mohor
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// Tmp version.
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//
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// Revision 1.2 2003/12/23 15:26:26 mohor
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// Small fix.
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//
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// Revision 1.1 2003/12/23 15:09:04 mohor
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// New directory structure. New version of the debug interface.
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//
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//
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//
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// synopsys translate_off
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// synopsys translate_off
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`include "timescale.v"
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`include "timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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`include "dbg_wb_defines.v"
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`include "dbg_wb_defines.v"
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| Line 260... |
Line 185... |
wire fifo_empty;
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wire fifo_empty;
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reg [7:0] mem [0:3];
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reg [7:0] mem [0:3];
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reg [2:0] mem_ptr_dsff;
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reg [2:0] mem_ptr_dsff;
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reg wishbone_ce_csff;
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reg wishbone_ce_csff;
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reg mem_ptr_init;
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reg mem_ptr_init;
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reg [`DBG_WB_CMD_LEN -1: 0] curr_cmd;
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reg [`DBG_WB_CMD_LEN_INT -1: 0] curr_cmd;
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wire curr_cmd_go;
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wire curr_cmd_go;
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reg curr_cmd_go_q;
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reg curr_cmd_go_q;
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wire curr_cmd_wr_comm;
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wire curr_cmd_wr_comm;
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wire curr_cmd_rd_comm;
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wire curr_cmd_rd_comm;
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wire acc_type_read;
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wire acc_type_read;
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| Line 391... |
Line 316... |
if (rst_i)
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if (rst_i)
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cmd_cnt <= {`DBG_WB_CMD_CNT_WIDTH{1'b0}};
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cmd_cnt <= {`DBG_WB_CMD_CNT_WIDTH{1'b0}};
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else if (update_dr_i)
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else if (update_dr_i)
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cmd_cnt <= {`DBG_WB_CMD_CNT_WIDTH{1'b0}};
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cmd_cnt <= {`DBG_WB_CMD_CNT_WIDTH{1'b0}};
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else if (cmd_cnt_en)
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else if (cmd_cnt_en)
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cmd_cnt <= cmd_cnt + 1'b1;
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cmd_cnt <= cmd_cnt + `DBG_WB_CMD_CNT_WIDTH'd1;
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end
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end
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|
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// Assigning current command
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// Assigning current command
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always @ (posedge tck_i or posedge rst_i)
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always @ (posedge tck_i or posedge rst_i)
|
begin
|
begin
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if (rst_i)
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if (rst_i)
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curr_cmd <= {`DBG_WB_CMD_LEN{1'b0}};
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curr_cmd <= {`DBG_WB_CMD_LEN_INT{1'b0}};
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else if (update_dr_i)
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else if (update_dr_i)
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curr_cmd <= {`DBG_WB_CMD_LEN{1'b0}};
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curr_cmd <= {`DBG_WB_CMD_LEN_INT{1'b0}};
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else if (cmd_cnt == (`DBG_WB_CMD_LEN -1))
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else if (cmd_cnt == (`DBG_WB_CMD_LEN_INT -1))
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curr_cmd <= {dr[`DBG_WB_CMD_LEN-2 :0], tdi_i};
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curr_cmd <= {dr[`DBG_WB_CMD_LEN_INT-2 :0], tdi_i};
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end
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end
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|
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// Assigning current command
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// Assigning current command
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always @ (posedge tck_i or posedge rst_i)
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always @ (posedge tck_i or posedge rst_i)
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| Line 437... |
Line 362... |
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// Address/length counter
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// Address/length counter
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always @ (posedge tck_i or posedge rst_i)
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always @ (posedge tck_i or posedge rst_i)
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begin
|
begin
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if (rst_i)
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if (rst_i)
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addr_len_cnt <= 6'h0;
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addr_len_cnt <= 6'd0;
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else if (update_dr_i)
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else if (update_dr_i)
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addr_len_cnt <= 6'h0;
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addr_len_cnt <= 6'd0;
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else if (addr_len_cnt_en)
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else if (addr_len_cnt_en)
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addr_len_cnt <= addr_len_cnt + 1'b1;
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addr_len_cnt <= addr_len_cnt + 6'd1;
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end
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end
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always @ (enable or data_cnt_end or cmd_cnt_end or curr_cmd_go or acc_type_write or acc_type_read or crc_cnt_end)
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always @ (enable or data_cnt_end or cmd_cnt_end or curr_cmd_go or acc_type_write or acc_type_read or crc_cnt_end)
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begin
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begin
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| Line 465... |
Line 390... |
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// Data counter
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// Data counter
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always @ (posedge tck_i or posedge rst_i)
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always @ (posedge tck_i or posedge rst_i)
|
begin
|
begin
|
if (rst_i)
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if (rst_i)
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data_cnt <= {`DBG_WB_DATA_CNT_WIDTH{1'b0}};
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data_cnt <= {`DBG_WB_DATA_CNT_WIDTH+1{1'b0}};
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else if (update_dr_i)
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else if (update_dr_i)
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data_cnt <= {`DBG_WB_DATA_CNT_WIDTH{1'b0}};
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data_cnt <= {`DBG_WB_DATA_CNT_WIDTH+1{1'b0}};
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else if (data_cnt_en)
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else if (data_cnt_en)
|
data_cnt <= data_cnt + 1'b1;
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data_cnt <= data_cnt + 1;
|
end
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end
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// Upper limit. Data counter counts until this value is reached.
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// Upper limit. Data counter counts until this value is reached.
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always @ (posedge tck_i or posedge rst_i)
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always @ (posedge tck_i or posedge rst_i)
|
begin
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begin
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if (rst_i)
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if (rst_i)
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data_cnt_limit <= {`DBG_WB_DATA_CNT_LIM_WIDTH{1'b0}};
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data_cnt_limit <= {`DBG_WB_DATA_CNT_LIM_WIDTH+1{1'b0}};
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else if (update_dr_i)
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else if (update_dr_i)
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data_cnt_limit <= len + 1'b1;
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data_cnt_limit <= len + 1;
|
end
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end
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always @ (enable or crc_cnt_end or curr_cmd_rd_comm or curr_cmd_wr_comm or curr_cmd_go or addr_len_cnt_end or data_cnt_end or acc_type_write or acc_type_read or cmd_cnt_end)
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always @ (enable or crc_cnt_end or curr_cmd_rd_comm or curr_cmd_wr_comm or curr_cmd_go or addr_len_cnt_end or data_cnt_end or acc_type_write or acc_type_read or cmd_cnt_end)
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begin
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begin
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| Line 508... |
Line 433... |
always @ (posedge tck_i or posedge rst_i)
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always @ (posedge tck_i or posedge rst_i)
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begin
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begin
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if (rst_i)
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if (rst_i)
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crc_cnt <= {`DBG_WB_CRC_CNT_WIDTH{1'b0}};
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crc_cnt <= {`DBG_WB_CRC_CNT_WIDTH{1'b0}};
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else if(crc_cnt_en)
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else if(crc_cnt_en)
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crc_cnt <= crc_cnt + 1'b1;
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crc_cnt <= crc_cnt + 1;
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else if (update_dr_i)
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else if (update_dr_i)
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crc_cnt <= {`DBG_WB_CRC_CNT_WIDTH{1'b0}};
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crc_cnt <= {`DBG_WB_CRC_CNT_WIDTH{1'b0}};
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end
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end
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|
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assign cmd_cnt_end = cmd_cnt == `DBG_WB_CMD_LEN;
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assign cmd_cnt_end = cmd_cnt == `DBG_WB_CMD_LEN;
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| Line 546... |
Line 471... |
if (rst_i)
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if (rst_i)
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status_cnt <= {`DBG_WB_STATUS_CNT_WIDTH{1'b0}};
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status_cnt <= {`DBG_WB_STATUS_CNT_WIDTH{1'b0}};
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else if (update_dr_i)
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else if (update_dr_i)
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status_cnt <= {`DBG_WB_STATUS_CNT_WIDTH{1'b0}};
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status_cnt <= {`DBG_WB_STATUS_CNT_WIDTH{1'b0}};
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else if (status_cnt_en)
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else if (status_cnt_en)
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status_cnt <= status_cnt + 1'b1;
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status_cnt <= status_cnt + `DBG_WB_STATUS_CNT_WIDTH'd1;
|
end
|
end
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always @ (enable or status_cnt_end or crc_cnt_end or curr_cmd_rd_comm or curr_cmd_wr_comm or curr_cmd_go or acc_type_write or acc_type_read or data_cnt_end or addr_len_cnt_end)
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always @ (enable or status_cnt_end or crc_cnt_end or curr_cmd_rd_comm or curr_cmd_wr_comm or curr_cmd_go or acc_type_write or acc_type_read or data_cnt_end or addr_len_cnt_end)
|
begin
|
begin
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| Line 613... |
Line 538... |
always @ (posedge tck_i or posedge rst_i)
|
always @ (posedge tck_i or posedge rst_i)
|
begin
|
begin
|
if (rst_i)
|
if (rst_i)
|
len_var <= {1'b0, {`DBG_WB_LEN_LEN{1'b0}}};
|
len_var <= {1'b0, {`DBG_WB_LEN_LEN{1'b0}}};
|
else if(update_dr_i)
|
else if(update_dr_i)
|
len_var <= len + 1'b1;
|
len_var <= len + 1;
|
else if (start_rd_tck)
|
else if (start_rd_tck)
|
begin
|
begin
|
case (acc_type) // synthesis parallel_case
|
case (acc_type) // synthesis parallel_case
|
`DBG_WB_READ8 :
|
`DBG_WB_READ8 :
|
if (len_var > 'd1)
|
if (len_var > 'd1)
|
len_var <= len_var - 1'd1;
|
len_var <= len_var - 1;
|
else
|
else
|
len_var <= {1'b0, {`DBG_WB_LEN_LEN{1'b0}}};
|
len_var <= {1'b0, {`DBG_WB_LEN_LEN{1'b0}}};
|
`DBG_WB_READ16:
|
`DBG_WB_READ16:
|
if (len_var > 'd2)
|
if (len_var > 'd2)
|
len_var <= len_var - 2'd2;
|
len_var <= len_var - 2;
|
else
|
else
|
len_var <= {1'b0, {`DBG_WB_LEN_LEN{1'b0}}};
|
len_var <= {1'b0, {`DBG_WB_LEN_LEN{1'b0}}};
|
`DBG_WB_READ32:
|
`DBG_WB_READ32:
|
if (len_var > 'd4)
|
if (len_var > 'd4)
|
len_var <= len_var - 3'd4;
|
len_var <= len_var - 4;
|
else
|
else
|
len_var <= {1'b0, {`DBG_WB_LEN_LEN{1'b0}}};
|
len_var <= {1'b0, {`DBG_WB_LEN_LEN{1'b0}}};
|
default: len_var <= {1'bx, {`DBG_WB_LEN_LEN{1'bx}}};
|
default: len_var <= {1'bx, {`DBG_WB_LEN_LEN{1'bx}}};
|
endcase
|
endcase
|
end
|
end
|
end
|
end
|
|
|
|
|
assign len_eq_0 = len_var == 'h0;
|
assign len_eq_0 = !(|len_var);
|
|
|
|
|
|
|
assign byte = data_cnt[2:0] == 3'd7;
|
assign byte = data_cnt[2:0] == 3'd7;
|
assign half = data_cnt[3:0] == 4'd15;
|
assign half = data_cnt[3:0] == 4'd15;
|
assign long = data_cnt[4:0] == 5'd31;
|
assign long = data_cnt[4:0] == 5'd31;
|
| Line 707... |
Line 633... |
else
|
else
|
begin
|
begin
|
start_wr_tck <= 1'b0;
|
start_wr_tck <= 1'b0;
|
end
|
end
|
end
|
end
|
|
default: begin
|
|
|
|
end
|
endcase
|
endcase
|
end
|
end
|
else
|
else
|
start_wr_tck <= 1'b0;
|
start_wr_tck <= 1'b0;
|
end
|
end
|
| Line 798... |
Line 727... |
|
|
// wb_adr_o logic
|
// wb_adr_o logic
|
always @ (posedge wb_clk_i or posedge rst_i)
|
always @ (posedge wb_clk_i or posedge rst_i)
|
begin
|
begin
|
if (rst_i)
|
if (rst_i)
|
wb_adr_dsff <= 32'h0;
|
wb_adr_dsff <= 32'd0;
|
else if (set_addr_wb && (!set_addr_wb_q)) // Setting starting address
|
else if (set_addr_wb && (!set_addr_wb_q)) // Setting starting address
|
wb_adr_dsff <= adr;
|
wb_adr_dsff <= adr;
|
else if (wb_ack_i)
|
else if (wb_ack_i)
|
begin
|
begin
|
if ((acc_type == `DBG_WB_WRITE8) || (acc_type == `DBG_WB_READ8))
|
if ((acc_type == `DBG_WB_WRITE8) || (acc_type == `DBG_WB_READ8))
|
wb_adr_dsff <= wb_adr_dsff + 1'd1;
|
wb_adr_dsff <= wb_adr_dsff + 32'd1;
|
else if ((acc_type == `DBG_WB_WRITE16) || (acc_type == `DBG_WB_READ16))
|
else if ((acc_type == `DBG_WB_WRITE16) || (acc_type == `DBG_WB_READ16))
|
wb_adr_dsff <= wb_adr_dsff + 2'd2;
|
wb_adr_dsff <= wb_adr_dsff + 32'd2;
|
else
|
else
|
wb_adr_dsff <= wb_adr_dsff + 3'd4;
|
wb_adr_dsff <= wb_adr_dsff + 32'd4;
|
end
|
end
|
end
|
end
|
|
|
|
|
assign wb_adr_o = wb_adr_dsff;
|
assign wb_adr_o = wb_adr_dsff;
|
| Line 1019... |
Line 948... |
else if(mem_ptr_init)
|
else if(mem_ptr_init)
|
mem_ptr_dsff <= 3'h0;
|
mem_ptr_dsff <= 3'h0;
|
else if (wb_ack_i)
|
else if (wb_ack_i)
|
begin
|
begin
|
if (acc_type == `DBG_WB_READ8)
|
if (acc_type == `DBG_WB_READ8)
|
mem_ptr_dsff <= mem_ptr_dsff + 1'd1;
|
mem_ptr_dsff <= mem_ptr_dsff + 3'd1;
|
else if (acc_type == `DBG_WB_READ16)
|
else if (acc_type == `DBG_WB_READ16)
|
mem_ptr_dsff <= mem_ptr_dsff + 2'd2;
|
mem_ptr_dsff <= mem_ptr_dsff + 3'd2;
|
end
|
end
|
end
|
end
|
|
|
|
|
// Logic for latching data that is read from wishbone
|
// Logic for latching data that is read from wishbone
|
| Line 1080... |
Line 1009... |
else if (update_dr_i)
|
else if (update_dr_i)
|
fifo_cnt <= 3'h0;
|
fifo_cnt <= 3'h0;
|
else if (wb_end_tck && (!wb_end_tck_q) && (!latch_data) && (!fifo_full)) // incrementing
|
else if (wb_end_tck && (!wb_end_tck_q) && (!latch_data) && (!fifo_full)) // incrementing
|
begin
|
begin
|
case (acc_type) // synthesis parallel_case
|
case (acc_type) // synthesis parallel_case
|
`DBG_WB_READ8 : fifo_cnt <= fifo_cnt + 1'd1;
|
`DBG_WB_READ8 : fifo_cnt <= fifo_cnt + 3'd1;
|
`DBG_WB_READ16: fifo_cnt <= fifo_cnt + 2'd2;
|
`DBG_WB_READ16: fifo_cnt <= fifo_cnt + 3'd2;
|
`DBG_WB_READ32: fifo_cnt <= fifo_cnt + 3'd4;
|
`DBG_WB_READ32: fifo_cnt <= fifo_cnt + 3'd4;
|
default: fifo_cnt <= 3'bxxx;
|
default: fifo_cnt <= 3'bxxx;
|
endcase
|
endcase
|
end
|
end
|
else if (!(wb_end_tck && (!wb_end_tck_q)) && latch_data && (!fifo_empty)) // decrementing
|
else if (!(wb_end_tck && (!wb_end_tck_q)) && latch_data && (!fifo_empty)) // decrementing
|
begin
|
begin
|
case (acc_type) // synthesis parallel_case
|
case (acc_type) // synthesis parallel_case
|
`DBG_WB_READ8 : fifo_cnt <= fifo_cnt - 1'd1;
|
`DBG_WB_READ8 : fifo_cnt <= fifo_cnt - 3'd1;
|
`DBG_WB_READ16: fifo_cnt <= fifo_cnt - 2'd2;
|
`DBG_WB_READ16: fifo_cnt <= fifo_cnt - 3'd2;
|
`DBG_WB_READ32: fifo_cnt <= fifo_cnt - 3'd4;
|
`DBG_WB_READ32: fifo_cnt <= fifo_cnt - 3'd4;
|
default: fifo_cnt <= 3'bxxx;
|
default: fifo_cnt <= 3'bxxx;
|
endcase
|
endcase
|
end
|
end
|
end
|
end
|
