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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [ethmac/] [eth_clockgen.v] - Diff between revs 570 and 618

Rev 570	Rev 618
Line 68...	Line 68...

`include "timescale.v"	`include "timescale.v"

`module eth_clockgen(Clk, Reset, Divider, MdcEn, MdcEn_n, Mdc);`	`module eth_clockgen(Clk, Reset, Divider, MdcEn, MdcEn_n, Mdc);`

`parameter Tp=1;`

`input Clk; // Input clock (Host clock)`	`input Clk; // Input clock (Host clock)`
`input Reset; // Reset signal`	`input Reset; // Reset signal`
`input [7:0] Divider; // Divider (input clock will be divided by the Divider[7:0])`	`input [7:0] Divider; // Divider (input clock will be divided by the Divider[7:0])`

`output Mdc; // Output clock`	`output Mdc; // Output clock`