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//// This file is part of the Ethernet IP core project ////
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//// This file is part of the Ethernet IP core project ////
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//// http://www.opencores.org/project,ethmac ////
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//// http://www.opencores.org/project,ethmac ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Igor Mohor (igorM@opencores.org) ////
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//// - Igor Mohor (igorM@opencores.org) ////
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//// - Julius Baxter (julius@opencores.org) ////
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//// ////
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//// ////
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//// All additional information is avaliable in the Readme.txt ////
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//// All additional information is avaliable in the Readme.txt ////
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//// file. ////
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//// file. ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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// Revision 1.3 2002/04/22 13:45:52 mohor
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// Generic ram or Xilinx ram can be used in fifo (selectable by setting
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// ETH_FIFO_XILINX in ethmac_defines.v).
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//
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// Revision 1.2 2002/03/25 13:33:04 mohor
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// When clear and read/write are active at the same time, cnt and pointers are
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// set to 1.
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//
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// Revision 1.1 2002/02/05 16:44:39 mohor
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// Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200
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// MHz. Statuses, overrun, control frame transmission and reception still need
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// to be fixed.
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//
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//
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`include "ethmac_defines.v"
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`include "ethmac_defines.v"
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`include "timescale.v"
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`include "timescale.v"
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module eth_fifo (data_in, data_out, clk, reset, write, read, clear, almost_full, full, almost_empty, empty, cnt);
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module eth_fifo (data_in, data_out, clk, reset, write, read, clear,
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almost_full, full, almost_empty, empty, cnt);
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parameter DATA_WIDTH = 32;
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parameter DATA_WIDTH = 32;
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parameter DEPTH = 8;
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parameter DEPTH = 8;
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parameter CNT_WIDTH = 4;
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parameter CNT_WIDTH = 3;
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input clk;
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input clk;
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input reset;
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input reset;
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input write;
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input write;
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input read;
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input read;
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| Line 92... |
Line 76... |
if(clear)
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if(clear)
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cnt <= { {(CNT_WIDTH-1){1'b0}}, read^write};
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cnt <= { {(CNT_WIDTH-1){1'b0}}, read^write};
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else
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else
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if(read ^ write)
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if(read ^ write)
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if(read)
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if(read)
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cnt <= cnt - 1'b1;
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cnt <= cnt - 1;
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else
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else
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cnt <= cnt + 1'b1;
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cnt <= cnt + 1;
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end
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end
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`ifdef ETH_FIFO_GENERIC
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`ifdef ETH_FIFO_GENERIC
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reg [DATA_WIDTH-1:0] fifo [0:DEPTH-1] /*synthesis syn_ramstyle = "no_rw_check"*/ ;
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reg [DATA_WIDTH-1:0] fifo [0:DEPTH-1] /*synthesis syn_ramstyle = "no_rw_check"*/ ;
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// This should make the synthesis tool infer RAMs
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// This should make the synthesis tool infer a RAM
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reg [CNT_WIDTH-2:0] waddr, raddr, raddr_reg;
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reg [CNT_WIDTH-1:0] waddr, raddr, raddr_reg;
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reg clear_reg; // Register the clear pulse
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reg clear_reg; // Register the clear pulse
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reg fallthrough_read;
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reg [CNT_WIDTH-1:0] fallthrough_read_addr;
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always @(posedge clk)
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if (reset)
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fallthrough_read <= 0;
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else
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fallthrough_read <= empty & write;
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always @(posedge clk)
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if (empty & write)
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fallthrough_read_addr <= waddr;
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always @(posedge clk)
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always @(posedge clk)
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if (reset)
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if (reset)
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waddr <= 0;
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waddr <= 0;
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else if (write)
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else if (write)
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waddr <= waddr + 1;
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waddr <= waddr + 1;
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wire raddr_reg_adv;
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reg read_reg;
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reg read_reg;
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always @(posedge clk)
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always @(posedge clk)
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read_reg <= read;
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read_reg <= read;
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// Advance the address after a read = first/next word fallthrough
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assign raddr_reg_adv = (cnt > 2) & read_reg;
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always @(posedge clk)
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always @(posedge clk)
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if (reset)
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if (reset)
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raddr <= 0;
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raddr <= 0;
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else if (clear)
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else if (clear)
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raddr <= waddr;
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raddr <= waddr;
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| Line 140... |
Line 134... |
clear_reg <= clear;
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clear_reg <= clear;
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always @ (posedge clk)
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always @ (posedge clk)
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if (read | clear_reg)
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if (read | clear_reg)
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raddr_reg <= raddr;
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raddr_reg <= raddr;
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else if (fallthrough_read) // To pulse RE for fall-through on Xilinx
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raddr_reg <= fallthrough_read_addr;
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assign data_out = fifo[raddr_reg];
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assign data_out = fifo[raddr_reg];
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always @(posedge clk)
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always @(posedge clk)
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Line 148... |
else if (final_read & read & !write)
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else if (final_read & read & !write)
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final_read <= ~final_read;
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final_read <= ~final_read;
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else if ((cnt == 1) & read & !write)
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else if ((cnt == 1) & read & !write)
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final_read <= 1; // Indicate last read data has been output
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final_read <= 1; // Indicate last read data has been output
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assign empty = ~(|cnt);
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assign empty = ~(|cnt);
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assign almost_empty = cnt==1;
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assign almost_empty = cnt==1;
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assign full = cnt == DEPTH;
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assign full = {{32-CNT_WIDTH{1'b0}},cnt} == (DEPTH-1);
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assign almost_full = &cnt[CNT_WIDTH-2:0];
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assign almost_full = &cnt[CNT_WIDTH-1:0];
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`else // !`ifdef ETH_FIFO_GENERIC
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`else // !`ifdef ETH_FIFO_GENERIC
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reg [CNT_WIDTH-2:0] read_pointer;
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reg [CNT_WIDTH-1:0] read_pointer;
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reg [CNT_WIDTH-2:0] write_pointer;
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reg [CNT_WIDTH-1:0] write_pointer;
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always @ (posedge clk or posedge reset)
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always @ (posedge clk or posedge reset)
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begin
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begin
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if(reset)
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if(reset)
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read_pointer <= 0;
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read_pointer <= 0;
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else
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else
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if(clear)
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if(clear)
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//read_pointer <= { {(CNT_WIDTH-2){1'b0}}, read};
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//read_pointer <= { {(CNT_WIDTH-1){1'b0}}, read};
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read_pointer <= { {(CNT_WIDTH-2){1'b0}}, 1'b1};
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read_pointer <= { {(CNT_WIDTH-1){1'b0}}, 1'b1};
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else
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else
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if(read & ~empty)
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if(read & ~empty)
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read_pointer <= read_pointer + 1'b1;
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read_pointer <= read_pointer + 1'b1;
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end
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end
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| Line 183... |
Line 178... |
begin
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begin
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if(reset)
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if(reset)
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write_pointer <= 0;
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write_pointer <= 0;
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else
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else
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if(clear)
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if(clear)
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write_pointer <= { {(CNT_WIDTH-2){1'b0}}, write};
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write_pointer <= { {(CNT_WIDTH-1){1'b0}}, write};
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else
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else
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if(write & ~full)
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if(write & ~full)
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write_pointer <= write_pointer + 1'b1;
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write_pointer <= write_pointer + 1'b1;
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end
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end
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| Line 215... |
Line 210... |
`endif // !`ifdef ETH_FIFO_XILINX
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`endif // !`ifdef ETH_FIFO_XILINX
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assign empty = ~(|cnt);
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assign empty = ~(|cnt);
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assign almost_empty = cnt == 1;
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assign almost_empty = cnt == 1;
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assign full = cnt == DEPTH;
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assign full = cnt == (DEPTH-1);
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assign almost_full = &cnt[CNT_WIDTH-2:0];
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assign almost_full = &cnt[CNT_WIDTH-1:0];
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`endif // !`ifdef ETH_FIFO_GENERIC
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`endif // !`ifdef ETH_FIFO_GENERIC
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