| Line 217... |
Line 217... |
wire [DATA_WIDTH-1:0] data_out0;
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wire [DATA_WIDTH-1:0] data_out0;
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wire [DATA_WIDTH-1:0] data_out1;
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wire [DATA_WIDTH-1:0] data_out1;
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wire [DATA_WIDTH-1:0] data_out2;
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wire [DATA_WIDTH-1:0] data_out2;
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wire [DATA_WIDTH-1:0] data_out3;
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wire [DATA_WIDTH-1:0] data_out3;
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wire ramsel0,ramsel1,ramsel2,ramsel3;
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wire we_ram0,we_ram1,we_ram2,we_ram3;
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assign ramsel0 = (read_pointer[5:4]==2'b00);
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assign we_ram0 = (write_pointer[5:4]==2'b00);
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assign ramsel1 = (read_pointer[5:4]==2'b01);
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assign we_ram1 = (write_pointer[5:4]==2'b01);
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assign ramsel2 = (read_pointer[5:4]==2'b10);
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assign we_ram2 = (write_pointer[5:4]==2'b10);
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assign ramsel3 = (read_pointer[5:4]==2'b11);
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assign we_ram3 = (write_pointer[5:4]==2'b11);
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assign data_out = ramsel3 ? data_out3 :
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assign data_out = (read_pointer[5:4]==2'b11) ? data_out3 :
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ramsel2 ? data_out2 :
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(read_pointer[5:4]==2'b10) ? data_out2 :
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ramsel1 ? data_out1 : data_out0;
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(read_pointer[5:4]==2'b01) ? data_out1 : data_out0;
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xilinx_dist_ram_16x32 fifo0
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xilinx_dist_ram_16x32 fifo0
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( .data_out(data_out0),
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( .data_out(data_out0),
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.we((write & ~full) & ramsel0),
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.we(write & ~full & we_ram0),
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.data_in(data_in),
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.data_in(data_in),
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.read_address( clear ? {CNT_WIDTH-1{1'b0}} : read_pointer[3:0]),
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.read_address( clear ? {CNT_WIDTH-1{1'b0}} : read_pointer[3:0]),
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.write_address(clear ? {CNT_WIDTH-1{1'b0}} : write_pointer[3:0]),
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.write_address(clear ? {CNT_WIDTH-1{1'b0}} : write_pointer[3:0]),
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.wclk(clk)
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.wclk(clk)
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);
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);
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xilinx_dist_ram_16x32 fifo1
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xilinx_dist_ram_16x32 fifo1
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( .data_out(data_out1),
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( .data_out(data_out1),
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.we(write & ~full & ramsel1),
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.we(write & ~full & we_ram1),
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.data_in(data_in),
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.data_in(data_in),
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.read_address( clear ? {CNT_WIDTH-1{1'b0}} : read_pointer[3:0]),
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.read_address( clear ? {CNT_WIDTH-1{1'b0}} : read_pointer[3:0]),
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.write_address(clear ? {CNT_WIDTH-1{1'b0}} : write_pointer[3:0]),
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.write_address(clear ? {CNT_WIDTH-1{1'b0}} : write_pointer[3:0]),
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.wclk(clk)
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.wclk(clk)
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);
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);
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xilinx_dist_ram_16x32 fifo2
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xilinx_dist_ram_16x32 fifo2
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( .data_out(data_out2),
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( .data_out(data_out2),
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.we(write & ~full & ramsel2),
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.we(write & ~full & we_ram2),
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.data_in(data_in),
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.data_in(data_in),
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.read_address( clear ? {CNT_WIDTH-1{1'b0}} : read_pointer[3:0]),
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.read_address( clear ? {CNT_WIDTH-1{1'b0}} : read_pointer[3:0]),
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.write_address(clear ? {CNT_WIDTH-1{1'b0}} : write_pointer[3:0]),
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.write_address(clear ? {CNT_WIDTH-1{1'b0}} : write_pointer[3:0]),
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.wclk(clk)
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.wclk(clk)
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);
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);
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xilinx_dist_ram_16x32 fifo3
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xilinx_dist_ram_16x32 fifo3
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( .data_out(data_out3),
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( .data_out(data_out3),
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.we(write & ~full & ramsel3),
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.we(write & ~full & we_ram3),
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.data_in(data_in),
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.data_in(data_in),
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.read_address( clear ? {CNT_WIDTH-1{1'b0}} : read_pointer[3:0]),
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.read_address( clear ? {CNT_WIDTH-1{1'b0}} : read_pointer[3:0]),
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.write_address(clear ? {CNT_WIDTH-1{1'b0}} : write_pointer[3:0]),
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.write_address(clear ? {CNT_WIDTH-1{1'b0}} : write_pointer[3:0]),
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.wclk(clk)
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.wclk(clk)
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);
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);
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