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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [ethmac/] [eth_fifo.v] - Diff between revs 502 and 530

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Line 64... Line 64... 
output  [CNT_WIDTH-1:0]   cnt;
 
output  [CNT_WIDTH-1:0]   cnt;
 
 
 
 
 
 
 
 
 
reg     [CNT_WIDTH-1:0]   read_pointer;
 
reg     [CNT_WIDTH-1:0]   read_pointer;
 
reg [CNT_WIDTH-1:0]        cnt;
 
reg [CNT_WIDTH-1:0]        cnt;
 
reg                       final_read;
 
 
 
 
 
 
 
always @ (posedge clk or posedge reset)
 
always @ (posedge clk or posedge reset)
 
begin
 
begin
 
  if(reset)
 
  if(reset)
 
    cnt <= 0;
 
    cnt <= 0;
Line 82... Line 81... 
    else
 
    else
 
      cnt <= cnt + 1;
 
      cnt <= cnt + 1;
 
end
 
end
 
 
 
 
 
 
 
 
 
 
 
   assign empty = ~(|cnt);
 
 
 
   assign almost_empty = cnt==1;
 
 
 
   assign full  = {{32-CNT_WIDTH{1'b0}},cnt} == (DEPTH-1);
 
 
 
   assign almost_full  = {{32-CNT_WIDTH{1'b0}},cnt} == (DEPTH-2);
 
 
 
 
 
 
 
 
 
`ifdef ETH_FIFO_GENERIC
 
`ifdef ETH_FIFO_GENERIC
 
 
 
 
 
   reg     [DATA_WIDTH-1:0]  fifo  [0:DEPTH-1] /*synthesis syn_ramstyle = "no_rw_check"*/ ;
 
   reg     [DATA_WIDTH-1:0]  fifo  [0:DEPTH-1] /*synthesis syn_ramstyle = "no_rw_check"*/ ;
 
 
 
 
 
 
 
 
Line 135... Line 140... 
     else if (fallthrough_read) // To pulse RE for fall-through on Xilinx
 
     else if (fallthrough_read) // To pulse RE for fall-through on Xilinx
 
       raddr_reg <= fallthrough_read_addr;
 
       raddr_reg <= fallthrough_read_addr;
 
 
 
 
 
   assign  data_out = fifo[raddr_reg];
 
   assign  data_out = fifo[raddr_reg];
 
 
 
 
 
 
 
 
 
   always @(posedge clk)
 
 
 
     if (reset)
 
 
 
       final_read <= 0;
 
 
 
     else if (final_read & read & !write)
 
 
 
       final_read <= ~final_read;
 
 
 
     else if ((cnt == 1) & read & !write)
 
 
 
       final_read <= 1; // Indicate last read data has been output
 
 
 
 
 
 
 
   assign empty = ~(|cnt);
 
 
 
   assign almost_empty = cnt==1;
 
 
 
   assign full  = {{32-CNT_WIDTH{1'b0}},cnt} == (DEPTH-1);
 
 
 
   //assign almost_full  = &cnt[CNT_WIDTH-1:0];
 
 
 
   assign almost_full  = {{32-CNT_WIDTH{1'b0}},cnt} == (DEPTH-2);
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
always @ (posedge clk or posedge reset)
 
always @ (posedge clk or posedge reset)
 
begin
 
begin
 
  if(reset)
 
  if(reset)
 
    read_pointer <= 0;
 
    read_pointer <= 0;
 
  else
 
  else
Line 193... Line 181... 
  if(clear)
 
  if(clear)
 
    write_pointer <= { {(CNT_WIDTH-1){1'b0}}, write};
 
    write_pointer <= { {(CNT_WIDTH-1){1'b0}}, write};
 
  else
 
  else
 
  if(write & ~full)
 
  if(write & ~full)
 
    write_pointer <= write_pointer + 1'b1;
 
    write_pointer <= write_pointer + 1'b1;
 
end
 
     end // always @ (posedge clk or posedge reset)
 
 
 
 
 
 
 
`endif // !`ifdef ETH_FIFO_GENERIC
 
 
 
 
 
 `ifdef ETH_FIFO_XILINX
 
 `ifdef ETH_FIFO_XILINX
 
 
 
 
 
  generate
 
  generate
 
     if (CNT_WIDTH==4)
 
     if (CNT_WIDTH==4)
Line 264... Line 254... 
              .read_address( clear ? {CNT_WIDTH-1{1'b0}} : read_pointer[3:0]),
 
              .read_address( clear ? {CNT_WIDTH-1{1'b0}} : read_pointer[3:0]),
 
              .write_address(clear ? {CNT_WIDTH-1{1'b0}} : write_pointer[3:0]),
 
              .write_address(clear ? {CNT_WIDTH-1{1'b0}} : write_pointer[3:0]),
 
              .wclk(clk)
 
              .wclk(clk)
 
              );
 
              );
 
       end // if (CNT_WIDTH==6)
 
       end // if (CNT_WIDTH==6)
 
 
 
 
 
  endgenerate
 
  endgenerate
 
 
 
 `endif //  `ifdef ETH_FIFO_XILINX
 
 
 
 
 
 
 
   `ifdef ETH_FIFO_RAMB18
 
 
 
 
 
 
 
   wire [8:0]                       read_pointer_to_xilinx_ram;
 
 
 
   wire [8:0]                       read_pointer_preincremented;
 
 
 
   assign read_pointer_preincremented = read_pointer + 1;
 
 
 
 
 
 
 
   assign read_pointer_to_xilinx_ram = (read) ?
 
 
 
                                       read_pointer_preincremented :
 
 
 
                                       read_pointer;
 
 
 
 
 
 
 
   wire [8:0]                       write_pointer_to_xilinx_ram;
 
 
 
   assign write_pointer_to_xilinx_ram = {{(9-CNT_WIDTH){1'b0}},write_pointer};
 
 
 
 
 
 
 
   // synthesis translate_off
 
 
 
   // Port A - Write
 
 
 
   // Port B - Rread
 
 
 
   BLK_MEM_GEN_V3_1 #(
 
 
 
                      .C_ADDRA_WIDTH(9),
 
 
 
                      .C_ADDRB_WIDTH(9),
 
 
 
                      .C_ALGORITHM(1),
 
 
 
                      .C_BYTE_SIZE(9),
 
 
 
                      .C_COMMON_CLK(0),
 
 
 
                      .C_DEFAULT_DATA("0"),
 
 
 
                      .C_DISABLE_WARN_BHV_COLL(0),
 
 
 
                      .C_DISABLE_WARN_BHV_RANGE(0),
 
 
 
                      .C_FAMILY("virtex5"),
 
 
 
                      .C_HAS_ENA(0),
 
 
 
                      .C_HAS_ENB(0),
 
 
 
                      .C_HAS_INJECTERR(0),
 
 
 
                      .C_HAS_MEM_OUTPUT_REGS_A(0),
 
 
 
                      .C_HAS_MEM_OUTPUT_REGS_B(0),
 
 
 
                      .C_HAS_MUX_OUTPUT_REGS_A(0),
 
 
 
                      .C_HAS_MUX_OUTPUT_REGS_B(0),
 
 
 
                      .C_HAS_REGCEA(0),
 
 
 
                      .C_HAS_REGCEB(0),
 
 
 
                      .C_HAS_RSTA(0),
 
 
 
                      .C_HAS_RSTB(0),
 
 
 
                      .C_INITA_VAL("0"),
 
 
 
                      .C_INITB_VAL("0"),
 
 
 
                      .C_INIT_FILE_NAME("no_coe_file_loaded"),
 
 
 
                      .C_LOAD_INIT_FILE(0),
 
 
 
                      .C_MEM_TYPE(1),
 
 
 
                      .C_MUX_PIPELINE_STAGES(0),
 
 
 
                      .C_PRIM_TYPE(1),
 
 
 
                      .C_READ_DEPTH_A(512),
 
 
 
                      .C_READ_DEPTH_B(512),
 
 
 
                      .C_READ_WIDTH_A(32),
 
 
 
                      .C_READ_WIDTH_B(32),
 
 
 
                      .C_RSTRAM_A(0),
 
 
 
                      .C_RSTRAM_B(0),
 
 
 
                      .C_RST_PRIORITY_A("CE"),
 
 
 
                      .C_RST_PRIORITY_B("CE"),
 
 
 
                      .C_RST_TYPE("SYNC"),
 
 
 
                      .C_SIM_COLLISION_CHECK("WARNING_ONLY"),
 
 
 
                      .C_USE_BYTE_WEA(0),
 
 
 
                      .C_USE_BYTE_WEB(0),
 
 
 
                      .C_USE_DEFAULT_DATA(0),
 
 
 
                      .C_USE_ECC(0),
 
 
 
                      .C_WEA_WIDTH(1),
 
 
 
                      .C_WEB_WIDTH(1),
 
 
 
                      .C_WRITE_DEPTH_A(512),
 
 
 
                      .C_WRITE_DEPTH_B(512),
 
 
 
                      .C_WRITE_MODE_A("WRITE_FIRST"),
 
 
 
                      .C_WRITE_MODE_B("READ_FIRST"),
 
 
 
                      .C_WRITE_WIDTH_A(32),
 
 
 
                      .C_WRITE_WIDTH_B(32),
 
 
 
                      .C_XDEVICEFAMILY("virtex5"))
 
 
 
   inst (
 
 
 
         .CLKA(clk),
 
 
 
         .WEA(write),
 
 
 
         .ADDRA(write_pointer_to_xilinx_ram),
 
 
 
         .DINA(data_in),
 
 
 
         .CLKB(clk),
 
 
 
         .ADDRB(read_pointer_to_xilinx_ram),
 
 
 
         .DOUTB(data_out),
 
 
 
         .RSTA(reset),
 
 
 
         .ENA(),
 
 
 
         .REGCEA(),
 
 
 
         .DOUTA(),
 
 
 
         .RSTB(),
 
 
 
         .ENB(),
 
 
 
         .REGCEB(),
 
 
 
         .WEB(),
 
 
 
         .DINB(),
 
 
 
         .INJECTSBITERR(),
 
 
 
         .INJECTDBITERR(),
 
 
 
         .SBITERR(),
 
 
 
         .DBITERR(),
 
 
 
         .RDADDRECC()
 
 
 
         );
 
 
 
   // synthesis translate_on
 
 
 
   `endif //  `ifdef ETH_FIFO_RAMB18
 
 
 
 
 
 
 
 
 
 
 
 
 
`else   // !ETH_FIFO_XILINX
 
 
 
`ifdef ETH_ALTERA_ALTSYNCRAM
 
`ifdef ETH_ALTERA_ALTSYNCRAM
 
  altera_dpram_16x32    altera_dpram_16x32_inst
 
  altera_dpram_16x32    altera_dpram_16x32_inst
 
  (
 
  (
 
        .data             (data_in),
 
        .data             (data_in),
 
        .wren             (write & ~full),
 
        .wren             (write & ~full),
Line 282... Line 364... 
        .rdaddress        (clear ? {CNT_WIDTH-1{1'b0}} : read_pointer ),
 
        .rdaddress        (clear ? {CNT_WIDTH-1{1'b0}} : read_pointer ),
 
        .clock            (clk),
 
        .clock            (clk),
 
        .q                (data_out)
 
        .q                (data_out)
 
  );  //exemplar attribute altera_dpram_16x32_inst NOOPT TRUE
 
  );  //exemplar attribute altera_dpram_16x32_inst NOOPT TRUE
 
`endif //  `ifdef ETH_ALTERA_ALTSYNCRAM
 
`endif //  `ifdef ETH_ALTERA_ALTSYNCRAM
 
`endif // !`ifdef ETH_FIFO_XILINX
 
 
 
 
 
 
 
 
 
 
 
assign empty = ~(|cnt);
 
 
 
assign almost_empty = cnt == 1;
 
 
 
assign full  = cnt == (DEPTH-1);
 
 
 
assign almost_full  = &cnt[CNT_WIDTH-1:0];
 
 
 
 
 
 
 
`endif // !`ifdef ETH_FIFO_GENERIC
 
 
 
 
 
 
 
 
 
 
 
 
 
endmodule // eth_fifo
 
 
 
 
 
endmodule
 
 
 
 
 
 
 
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