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//////////////////////////////////////////////////////////////////////
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//// ////
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//// eth_maccontrol.v ////
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//// ////
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//// This file is part of the Ethernet IP core project ////
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//// http://www.opencores.org/project,ethmac ////
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//// ////
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//// Author(s): ////
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//// - Igor Mohor (igorM@opencores.org) ////
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//// ////
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//// All additional information is avaliable in the Readme.txt ////
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//// file. ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2001 Authors ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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// Revision 1.6 2002/11/22 01:57:06 mohor
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// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
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// synchronized.
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//
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// Revision 1.5 2002/11/21 00:14:39 mohor
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// TxDone and TxAbort changed so they're not propagated to the wishbone
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// module when control frame is transmitted.
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//
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// Revision 1.4 2002/11/19 17:37:32 mohor
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// When control frame (PAUSE) was sent, status was written in the
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// eth_wishbone module and both TXB and TXC interrupts were set. Fixed.
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// Only TXC interrupt is set.
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//
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// Revision 1.3 2002/01/23 10:28:16 mohor
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// Link in the header changed.
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//
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// Revision 1.2 2001/10/19 08:43:51 mohor
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// eth_timescale.v changed to timescale.v This is done because of the
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// simulation of the few cores in a one joined project.
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//
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// Revision 1.1 2001/08/06 14:44:29 mohor
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// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
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// Include files fixed to contain no path.
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// File names and module names changed ta have a eth_ prologue in the name.
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// File eth_timescale.v is used to define timescale
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// All pin names on the top module are changed to contain _I, _O or _OE at the end.
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// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
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// and Mdo_OE. The bidirectional signal must be created on the top level. This
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// is done due to the ASIC tools.
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//
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// Revision 1.1 2001/07/30 21:23:42 mohor
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// Directory structure changed. Files checked and joind together.
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//
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// Revision 1.1 2001/07/03 12:51:54 mohor
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// Initial release of the MAC Control module.
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//
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//
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//
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//
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`include "timescale.v"
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module eth_maccontrol (MTxClk, MRxClk, TxReset, RxReset, TPauseRq, TxDataIn, TxStartFrmIn, TxUsedDataIn,
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TxEndFrmIn, TxDoneIn, TxAbortIn, RxData, RxValid, RxStartFrm, RxEndFrm, ReceiveEnd,
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ReceivedPacketGood, ReceivedLengthOK, TxFlow, RxFlow, DlyCrcEn, TxPauseTV,
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MAC, PadIn, PadOut, CrcEnIn, CrcEnOut, TxDataOut, TxStartFrmOut, TxEndFrmOut,
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TxDoneOut, TxAbortOut, TxUsedDataOut, WillSendControlFrame, TxCtrlEndFrm,
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ReceivedPauseFrm, ControlFrmAddressOK, SetPauseTimer, r_PassAll, RxStatusWriteLatched_sync2
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);
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parameter Tp = 1;
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input MTxClk; // Transmit clock (from PHY)
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input MRxClk; // Receive clock (from PHY)
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input TxReset; // Transmit reset
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input RxReset; // Receive reset
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input TPauseRq; // Transmit control frame (from host)
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input [7:0] TxDataIn; // Transmit packet data byte (from host)
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input TxStartFrmIn; // Transmit packet start frame input (from host)
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input TxUsedDataIn; // Transmit packet used data (from TxEthMAC)
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input TxEndFrmIn; // Transmit packet end frame input (from host)
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input TxDoneIn; // Transmit packet done (from TxEthMAC)
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input TxAbortIn; // Transmit packet abort (input from TxEthMAC)
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input PadIn; // Padding (input from registers)
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input CrcEnIn; // Crc append (input from registers)
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input [7:0] RxData; // Receive Packet Data (from RxEthMAC)
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input RxValid; // Received a valid packet
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input RxStartFrm; // Receive packet start frame (input from RxEthMAC)
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input RxEndFrm; // Receive packet end frame (input from RxEthMAC)
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input ReceiveEnd; // End of receiving of the current packet (input from RxEthMAC)
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input ReceivedPacketGood; // Received packet is good
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input ReceivedLengthOK; // Length of the received packet is OK
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input TxFlow; // Tx flow control (from registers)
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input RxFlow; // Rx flow control (from registers)
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input DlyCrcEn; // Delayed CRC enabled (from registers)
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input [15:0] TxPauseTV; // Transmit Pause Timer Value (from registers)
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input [47:0] MAC; // MAC address (from registers)
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input RxStatusWriteLatched_sync2;
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input r_PassAll;
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output [7:0] TxDataOut; // Transmit Packet Data (to TxEthMAC)
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output TxStartFrmOut; // Transmit packet start frame (output to TxEthMAC)
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output TxEndFrmOut; // Transmit packet end frame (output to TxEthMAC)
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output TxDoneOut; // Transmit packet done (to host)
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output TxAbortOut; // Transmit packet aborted (to host)
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output TxUsedDataOut; // Transmit packet used data (to host)
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output PadOut; // Padding (output to TxEthMAC)
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output CrcEnOut; // Crc append (output to TxEthMAC)
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output WillSendControlFrame;
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output TxCtrlEndFrm;
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output ReceivedPauseFrm;
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output ControlFrmAddressOK;
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output SetPauseTimer;
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reg TxUsedDataOutDetected;
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reg TxAbortInLatched;
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reg TxDoneInLatched;
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reg MuxedDone;
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reg MuxedAbort;
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wire Pause;
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wire TxCtrlStartFrm;
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wire [7:0] ControlData;
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wire CtrlMux;
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wire SendingCtrlFrm; // Sending Control Frame (enables padding and CRC)
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wire BlockTxDone;
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// Signal TxUsedDataOut was detected (a transfer is already in progress)
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always @ (posedge MTxClk or posedge TxReset)
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begin
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if(TxReset)
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TxUsedDataOutDetected <= 1'b0;
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else
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if(TxDoneIn | TxAbortIn)
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TxUsedDataOutDetected <= 1'b0;
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else
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if(TxUsedDataOut)
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TxUsedDataOutDetected <= 1'b1;
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end
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// Latching variables
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always @ (posedge MTxClk or posedge TxReset)
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begin
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if(TxReset)
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begin
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TxAbortInLatched <= 1'b0;
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TxDoneInLatched <= 1'b0;
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end
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else
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begin
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TxAbortInLatched <= TxAbortIn;
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TxDoneInLatched <= TxDoneIn;
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end
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end
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// Generating muxed abort signal
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always @ (posedge MTxClk or posedge TxReset)
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begin
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if(TxReset)
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MuxedAbort <= 1'b0;
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else
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if(TxStartFrmIn)
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MuxedAbort <= 1'b0;
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else
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if(TxAbortIn & ~TxAbortInLatched & TxUsedDataOutDetected)
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MuxedAbort <= 1'b1;
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end
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// Generating muxed done signal
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always @ (posedge MTxClk or posedge TxReset)
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begin
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if(TxReset)
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MuxedDone <= 1'b0;
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else
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if(TxStartFrmIn)
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MuxedDone <= 1'b0;
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else
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if(TxDoneIn & (~TxDoneInLatched) & TxUsedDataOutDetected)
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MuxedDone <= 1'b1;
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end
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// TxDoneOut
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assign TxDoneOut = CtrlMux? ((~TxStartFrmIn) & (~BlockTxDone) & MuxedDone) :
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((~TxStartFrmIn) & (~BlockTxDone) & TxDoneIn);
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// TxAbortOut
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assign TxAbortOut = CtrlMux? ((~TxStartFrmIn) & (~BlockTxDone) & MuxedAbort) :
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((~TxStartFrmIn) & (~BlockTxDone) & TxAbortIn);
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// TxUsedDataOut
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assign TxUsedDataOut = ~CtrlMux & TxUsedDataIn;
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// TxStartFrmOut
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assign TxStartFrmOut = CtrlMux? TxCtrlStartFrm : (TxStartFrmIn & ~Pause);
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// TxEndFrmOut
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assign TxEndFrmOut = CtrlMux? TxCtrlEndFrm : TxEndFrmIn;
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// TxDataOut[7:0]
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assign TxDataOut[7:0] = CtrlMux? ControlData[7:0] : TxDataIn[7:0];
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// PadOut
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assign PadOut = PadIn | SendingCtrlFrm;
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// CrcEnOut
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assign CrcEnOut = CrcEnIn | SendingCtrlFrm;
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// Connecting receivecontrol module
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eth_receivecontrol receivecontrol1
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(
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.MTxClk(MTxClk), .MRxClk(MRxClk), .TxReset(TxReset), .RxReset(RxReset), .RxData(RxData),
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.RxValid(RxValid), .RxStartFrm(RxStartFrm), .RxEndFrm(RxEndFrm), .RxFlow(RxFlow),
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.ReceiveEnd(ReceiveEnd), .MAC(MAC), .DlyCrcEn(DlyCrcEn), .TxDoneIn(TxDoneIn),
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.TxAbortIn(TxAbortIn), .TxStartFrmOut(TxStartFrmOut), .ReceivedLengthOK(ReceivedLengthOK),
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.ReceivedPacketGood(ReceivedPacketGood), .TxUsedDataOutDetected(TxUsedDataOutDetected),
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.Pause(Pause), .ReceivedPauseFrm(ReceivedPauseFrm), .AddressOK(ControlFrmAddressOK),
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.r_PassAll(r_PassAll), .RxStatusWriteLatched_sync2(RxStatusWriteLatched_sync2), .SetPauseTimer(SetPauseTimer)
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);
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eth_transmitcontrol transmitcontrol1
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(
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.MTxClk(MTxClk), .TxReset(TxReset), .TxUsedDataIn(TxUsedDataIn), .TxUsedDataOut(TxUsedDataOut),
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.TxDoneIn(TxDoneIn), .TxAbortIn(TxAbortIn), .TxStartFrmIn(TxStartFrmIn), .TPauseRq(TPauseRq),
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.TxUsedDataOutDetected(TxUsedDataOutDetected), .TxFlow(TxFlow), .DlyCrcEn(DlyCrcEn), .TxPauseTV(TxPauseTV),
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.MAC(MAC), .TxCtrlStartFrm(TxCtrlStartFrm), .TxCtrlEndFrm(TxCtrlEndFrm), .SendingCtrlFrm(SendingCtrlFrm),
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.CtrlMux(CtrlMux), .ControlData(ControlData), .WillSendControlFrame(WillSendControlFrame), .BlockTxDone(BlockTxDone)
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);
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endmodule
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No newline at end of file
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No newline at end of file
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