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//////////////////////////////////////////////////////////////////////
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//// ////
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//// eth_macstatus.v ////
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//// ////
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//// This file is part of the Ethernet IP core project ////
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//// http://www.opencores.org/project,ethmac ////
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//// ////
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//// Author(s): ////
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//// - Igor Mohor (igorM@opencores.org) ////
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//// ////
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//// All additional information is available in the Readme.txt ////
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//// file. ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2001, 2002 Authors ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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// Revision 1.16 2005/02/21 10:42:11 igorm
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// Defer indication fixed.
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//
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// Revision 1.15 2003/01/30 13:28:19 tadejm
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// Defer indication changed.
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//
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// Revision 1.14 2002/11/22 01:57:06 mohor
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// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
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// synchronized.
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//
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// Revision 1.13 2002/11/13 22:30:58 tadejm
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// Late collision is reported only when not in the full duplex.
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// Sample is taken (for status) as soon as MRxDV is not valid (regardless
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// of the received byte cnt).
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//
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// Revision 1.12 2002/09/12 14:50:16 mohor
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// CarrierSenseLost bug fixed when operating in full duplex mode.
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//
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// Revision 1.11 2002/09/04 18:38:03 mohor
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// CarrierSenseLost status is not set when working in loopback mode.
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//
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// Revision 1.10 2002/07/25 18:17:46 mohor
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// InvalidSymbol generation changed.
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//
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// Revision 1.9 2002/04/22 13:51:44 mohor
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// Short frame and ReceivedLengthOK were not detected correctly.
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//
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// Revision 1.8 2002/02/18 10:40:17 mohor
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// Small fixes.
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//
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// Revision 1.7 2002/02/15 17:07:39 mohor
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// Status was not written correctly when frames were discarted because of
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// address mismatch.
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//
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// Revision 1.6 2002/02/11 09:18:21 mohor
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// Tx status is written back to the BD.
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//
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// Revision 1.5 2002/02/08 16:21:54 mohor
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// Rx status is written back to the BD.
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//
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// Revision 1.4 2002/01/23 10:28:16 mohor
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// Link in the header changed.
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//
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// Revision 1.3 2001/10/19 08:43:51 mohor
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// eth_timescale.v changed to timescale.v This is done because of the
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// simulation of the few cores in a one joined project.
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//
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// Revision 1.2 2001/09/11 14:17:00 mohor
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// Few little NCSIM warnings fixed.
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//
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// Revision 1.1 2001/08/06 14:44:29 mohor
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// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
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// Include files fixed to contain no path.
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// File names and module names changed ta have a eth_ prologue in the name.
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// File eth_timescale.v is used to define timescale
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// All pin names on the top module are changed to contain _I, _O or _OE at the end.
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// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
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// and Mdo_OE. The bidirectional signal must be created on the top level. This
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// is done due to the ASIC tools.
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//
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// Revision 1.1 2001/07/30 21:23:42 mohor
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// Directory structure changed. Files checked and joind together.
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//
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//
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//
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//
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//
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`include "timescale.v"
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module eth_macstatus(
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MRxClk, Reset, ReceivedLengthOK, ReceiveEnd, ReceivedPacketGood, RxCrcError,
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MRxErr, MRxDV, RxStateSFD, RxStateData, RxStatePreamble, RxStateIdle, Transmitting,
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RxByteCnt, RxByteCntEq0, RxByteCntGreat2, RxByteCntMaxFrame,
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InvalidSymbol, MRxD, LatchedCrcError, Collision, CollValid, RxLateCollision,
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r_RecSmall, r_MinFL, r_MaxFL, ShortFrame, DribbleNibble, ReceivedPacketTooBig, r_HugEn,
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LoadRxStatus, StartTxDone, StartTxAbort, RetryCnt, RetryCntLatched, MTxClk, MaxCollisionOccured,
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RetryLimit, LateCollision, LateCollLatched, DeferIndication, DeferLatched, RstDeferLatched, TxStartFrm,
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StatePreamble, StateData, CarrierSense, CarrierSenseLost, TxUsedData, LatchedMRxErr, Loopback,
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r_FullD
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);
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parameter Tp = 1;
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input MRxClk;
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input Reset;
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input RxCrcError;
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input MRxErr;
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input MRxDV;
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input RxStateSFD;
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input [1:0] RxStateData;
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input RxStatePreamble;
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input RxStateIdle;
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input Transmitting;
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input [15:0] RxByteCnt;
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input RxByteCntEq0;
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input RxByteCntGreat2;
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input RxByteCntMaxFrame;
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input [3:0] MRxD;
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input Collision;
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input [5:0] CollValid;
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input r_RecSmall;
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input [15:0] r_MinFL;
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input [15:0] r_MaxFL;
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input r_HugEn;
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input StartTxDone;
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input StartTxAbort;
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input [3:0] RetryCnt;
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input MTxClk;
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input MaxCollisionOccured;
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input LateCollision;
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input DeferIndication;
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input TxStartFrm;
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input StatePreamble;
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input [1:0] StateData;
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input CarrierSense;
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input TxUsedData;
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input Loopback;
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input r_FullD;
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output ReceivedLengthOK;
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output ReceiveEnd;
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output ReceivedPacketGood;
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output InvalidSymbol;
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output LatchedCrcError;
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output RxLateCollision;
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output ShortFrame;
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output DribbleNibble;
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output ReceivedPacketTooBig;
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output LoadRxStatus;
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output [3:0] RetryCntLatched;
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output RetryLimit;
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output LateCollLatched;
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output DeferLatched;
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input RstDeferLatched;
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output CarrierSenseLost;
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output LatchedMRxErr;
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reg ReceiveEnd;
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reg LatchedCrcError;
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reg LatchedMRxErr;
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reg LoadRxStatus;
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reg InvalidSymbol;
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reg [3:0] RetryCntLatched;
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reg RetryLimit;
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reg LateCollLatched;
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reg DeferLatched;
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reg CarrierSenseLost;
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wire TakeSample;
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wire SetInvalidSymbol; // Invalid symbol was received during reception in 100Mbps
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// Crc error
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always @ (posedge MRxClk or posedge Reset)
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begin
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if(Reset)
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LatchedCrcError <= 1'b0;
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else
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if(RxStateSFD)
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LatchedCrcError <= 1'b0;
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else
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if(RxStateData[0])
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LatchedCrcError <= RxCrcError & ~RxByteCntEq0;
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end
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// LatchedMRxErr
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always @ (posedge MRxClk or posedge Reset)
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begin
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if(Reset)
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LatchedMRxErr <= 1'b0;
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else
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if(MRxErr & MRxDV & (RxStatePreamble | RxStateSFD | (|RxStateData) | RxStateIdle & ~Transmitting))
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LatchedMRxErr <= 1'b1;
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else
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LatchedMRxErr <= 1'b0;
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end
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// ReceivedPacketGood
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assign ReceivedPacketGood = ~LatchedCrcError;
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// ReceivedLengthOK
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assign ReceivedLengthOK = RxByteCnt[15:0] >= r_MinFL[15:0] & RxByteCnt[15:0] <= r_MaxFL[15:0];
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// Time to take a sample
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//assign TakeSample = |RxStateData & ~MRxDV & RxByteCntGreat2 |
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assign TakeSample = (|RxStateData) & (~MRxDV) |
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RxStateData[0] & MRxDV & RxByteCntMaxFrame;
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// LoadRxStatus
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always @ (posedge MRxClk or posedge Reset)
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begin
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if(Reset)
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LoadRxStatus <= 1'b0;
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else
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LoadRxStatus <= TakeSample;
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end
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// ReceiveEnd
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always @ (posedge MRxClk or posedge Reset)
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begin
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if(Reset)
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ReceiveEnd <= 1'b0;
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else
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ReceiveEnd <= LoadRxStatus;
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end
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// Invalid Symbol received during 100Mbps mode
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assign SetInvalidSymbol = MRxDV & MRxErr & MRxD[3:0] == 4'he;
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// InvalidSymbol
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always @ (posedge MRxClk or posedge Reset)
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begin
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if(Reset)
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InvalidSymbol <= 1'b0;
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else
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if(LoadRxStatus & ~SetInvalidSymbol)
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InvalidSymbol <= 1'b0;
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else
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if(SetInvalidSymbol)
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InvalidSymbol <= 1'b1;
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end
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// Late Collision
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reg RxLateCollision;
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reg RxColWindow;
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// Collision Window
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always @ (posedge MRxClk or posedge Reset)
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begin
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if(Reset)
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RxLateCollision <= 1'b0;
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else
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if(LoadRxStatus)
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RxLateCollision <= 1'b0;
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else
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if(Collision & (~r_FullD) & (~RxColWindow | r_RecSmall))
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RxLateCollision <= 1'b1;
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end
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// Collision Window
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always @ (posedge MRxClk or posedge Reset)
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begin
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if(Reset)
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RxColWindow <= 1'b1;
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else
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if(~Collision & RxByteCnt[5:0] == CollValid[5:0] & RxStateData[1])
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RxColWindow <= 1'b0;
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else
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if(RxStateIdle)
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RxColWindow <= 1'b1;
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end
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// ShortFrame
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reg ShortFrame;
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always @ (posedge MRxClk or posedge Reset)
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begin
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if(Reset)
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ShortFrame <= 1'b0;
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else
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if(LoadRxStatus)
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ShortFrame <= 1'b0;
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else
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if(TakeSample)
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ShortFrame <= RxByteCnt[15:0] < r_MinFL[15:0];
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end
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// DribbleNibble
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reg DribbleNibble;
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always @ (posedge MRxClk or posedge Reset)
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begin
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if(Reset)
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DribbleNibble <= 1'b0;
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else
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if(RxStateSFD)
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DribbleNibble <= 1'b0;
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else
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if(~MRxDV & RxStateData[1])
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DribbleNibble <= 1'b1;
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end
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reg ReceivedPacketTooBig;
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always @ (posedge MRxClk or posedge Reset)
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begin
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if(Reset)
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ReceivedPacketTooBig <= 1'b0;
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else
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if(LoadRxStatus)
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ReceivedPacketTooBig <= 1'b0;
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else
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if(TakeSample)
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ReceivedPacketTooBig <= ~r_HugEn & RxByteCnt[15:0] > r_MaxFL[15:0];
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end
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// Latched Retry counter for tx status
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always @ (posedge MTxClk or posedge Reset)
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begin
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if(Reset)
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RetryCntLatched <= 4'h0;
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else
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if(StartTxDone | StartTxAbort)
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RetryCntLatched <= RetryCnt;
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end
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// Latched Retransmission limit
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always @ (posedge MTxClk or posedge Reset)
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begin
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if(Reset)
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RetryLimit <= 1'h0;
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else
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if(StartTxDone | StartTxAbort)
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RetryLimit <= MaxCollisionOccured;
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end
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// Latched Late Collision
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always @ (posedge MTxClk or posedge Reset)
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begin
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if(Reset)
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LateCollLatched <= 1'b0;
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else
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if(StartTxDone | StartTxAbort)
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LateCollLatched <= LateCollision;
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end
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// Latched Defer state
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always @ (posedge MTxClk or posedge Reset)
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begin
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if(Reset)
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DeferLatched <= 1'b0;
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else
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if(DeferIndication)
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DeferLatched <= 1'b1;
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else
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if(RstDeferLatched)
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DeferLatched <= 1'b0;
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end
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// CarrierSenseLost
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always @ (posedge MTxClk or posedge Reset)
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begin
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if(Reset)
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CarrierSenseLost <= 1'b0;
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else
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if((StatePreamble | (|StateData)) & ~CarrierSense & ~Loopback & ~Collision & ~r_FullD)
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CarrierSenseLost <= 1'b1;
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else
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if(TxStartFrm)
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CarrierSenseLost <= 1'b0;
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end
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endmodule
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