URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [ethmac/] [eth_miim.v] - Diff between revs 570 and 618

Rev 570	Rev 618
Line 133...	Line 133...

`output WCtrlDataStart; // This signals resets the WCTRLDATA bit in the MIIM Command register`	`output WCtrlDataStart; // This signals resets the WCTRLDATA bit in the MIIM Command register`
`output RStatStart; // This signal resets the RSTAT BIT in the MIIM Command register`	`output RStatStart; // This signal resets the RSTAT BIT in the MIIM Command register`
`output UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data`	`output UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data`

`parameter Tp = 1;`


`reg Nvalid;`	`reg Nvalid;`
`reg EndBusy_d; // Pre-end Busy signal`	`reg EndBusy_d; // Pre-end Busy signal`
`reg EndBusy; // End Busy signal (stops the operation in progress)`	`reg EndBusy; // End Busy signal (stops the operation in progress)`