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Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [ethmac/] [eth_outputcontrol.v] - Diff between revs 570 and 618

Rev 570	Rev 618
Line 68...	Line 68...

`include "timescale.v"	`include "timescale.v"

`module eth_outputcontrol(Clk, Reset, InProgress, ShiftedBit, BitCounter, WriteOp, NoPre, MdcEn_n, Mdo, MdoEn);`	`module eth_outputcontrol(Clk, Reset, InProgress, ShiftedBit, BitCounter, WriteOp, NoPre, MdcEn_n, Mdo, MdoEn);`

`parameter Tp = 1;`

`input Clk; // Host Clock`	`input Clk; // Host Clock`
`input Reset; // General Reset`	`input Reset; // General Reset`
`input WriteOp; // Write Operation Latch (When asserted, write operation is in progress)`	`input WriteOp; // Write Operation Latch (When asserted, write operation is in progress)`
`input NoPre; // No Preamble (no 32-bit preamble)`	`input NoPre; // No Preamble (no 32-bit preamble)`
`input InProgress; // Operation in progress`	`input InProgress; // Operation in progress`