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`include "timescale.v"
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`include "timescale.v"
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module eth_random (MTxClk, Reset, StateJam, StateJam_q, RetryCnt, NibCnt, ByteCnt,
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module eth_random (MTxClk, Reset, StateJam, StateJam_q, RetryCnt, NibCnt, ByteCnt,
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RandomEq0, RandomEqByteCnt);
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RandomEq0, RandomEqByteCnt);
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parameter Tp = 1;
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input MTxClk;
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input MTxClk;
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input Reset;
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input Reset;
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input StateJam;
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input StateJam;
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input StateJam_q;
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input StateJam_q;
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input [3:0] RetryCnt;
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input [3:0] RetryCnt;
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