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//////////////////////////////////////////////////////////////////////
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//// ////
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//// eth_receivecontrol.v ////
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//// ////
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//// This file is part of the Ethernet IP core project ////
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//// http://www.opencores.org/project,ethmac ////
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//// ////
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//// Author(s): ////
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//// - Igor Mohor (igorM@opencores.org) ////
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//// ////
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//// All additional information is avaliable in the Readme.txt ////
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//// file. ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2001 Authors ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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// Revision 1.4 2002/11/22 01:57:06 mohor
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// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
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// synchronized.
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//
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// Revision 1.3 2002/01/23 10:28:16 mohor
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// Link in the header changed.
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//
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// Revision 1.2 2001/10/19 08:43:51 mohor
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// eth_timescale.v changed to timescale.v This is done because of the
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// simulation of the few cores in a one joined project.
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//
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// Revision 1.1 2001/08/06 14:44:29 mohor
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// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
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// Include files fixed to contain no path.
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// File names and module names changed ta have a eth_ prologue in the name.
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// File eth_timescale.v is used to define timescale
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// All pin names on the top module are changed to contain _I, _O or _OE at the end.
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// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
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// and Mdo_OE. The bidirectional signal must be created on the top level. This
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// is done due to the ASIC tools.
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//
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// Revision 1.1 2001/07/30 21:23:42 mohor
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// Directory structure changed. Files checked and joind together.
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//
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// Revision 1.1 2001/07/03 12:51:54 mohor
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// Initial release of the MAC Control module.
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//
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//
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//
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//
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//
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`include "timescale.v"
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module eth_receivecontrol (MTxClk, MRxClk, TxReset, RxReset, RxData, RxValid, RxStartFrm,
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RxEndFrm, RxFlow, ReceiveEnd, MAC, DlyCrcEn, TxDoneIn,
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TxAbortIn, TxStartFrmOut, ReceivedLengthOK, ReceivedPacketGood,
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TxUsedDataOutDetected, Pause, ReceivedPauseFrm, AddressOK,
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RxStatusWriteLatched_sync2, r_PassAll, SetPauseTimer
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);
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parameter Tp = 1;
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input MTxClk;
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input MRxClk;
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input TxReset;
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input RxReset;
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input [7:0] RxData;
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input RxValid;
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input RxStartFrm;
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input RxEndFrm;
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input RxFlow;
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input ReceiveEnd;
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input [47:0]MAC;
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input DlyCrcEn;
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input TxDoneIn;
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input TxAbortIn;
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input TxStartFrmOut;
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input ReceivedLengthOK;
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input ReceivedPacketGood;
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input TxUsedDataOutDetected;
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input RxStatusWriteLatched_sync2;
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input r_PassAll;
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output Pause;
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output ReceivedPauseFrm;
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output AddressOK;
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output SetPauseTimer;
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reg Pause;
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reg AddressOK; // Multicast or unicast address detected
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reg TypeLengthOK; // Type/Length field contains 0x8808
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reg DetectionWindow; // Detection of the PAUSE frame is possible within this window
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reg OpCodeOK; // PAUSE opcode detected (0x0001)
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reg [2:0] DlyCrcCnt;
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reg [4:0] ByteCnt;
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reg [15:0] AssembledTimerValue;
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reg [15:0] LatchedTimerValue;
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reg ReceivedPauseFrm;
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reg ReceivedPauseFrmWAddr;
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reg PauseTimerEq0_sync1;
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reg PauseTimerEq0_sync2;
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reg [15:0] PauseTimer;
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reg Divider2;
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reg [5:0] SlotTimer;
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wire [47:0] ReservedMulticast; // 0x0180C2000001
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wire [15:0] TypeLength; // 0x8808
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wire ResetByteCnt; //
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wire IncrementByteCnt; //
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wire ByteCntEq0; // ByteCnt = 0
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wire ByteCntEq1; // ByteCnt = 1
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wire ByteCntEq2; // ByteCnt = 2
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wire ByteCntEq3; // ByteCnt = 3
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wire ByteCntEq4; // ByteCnt = 4
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wire ByteCntEq5; // ByteCnt = 5
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wire ByteCntEq12; // ByteCnt = 12
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wire ByteCntEq13; // ByteCnt = 13
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wire ByteCntEq14; // ByteCnt = 14
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wire ByteCntEq15; // ByteCnt = 15
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wire ByteCntEq16; // ByteCnt = 16
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wire ByteCntEq17; // ByteCnt = 17
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wire ByteCntEq18; // ByteCnt = 18
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wire DecrementPauseTimer; //
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wire PauseTimerEq0; //
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wire ResetSlotTimer; //
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wire IncrementSlotTimer; //
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wire SlotFinished; //
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// Reserved multicast address and Type/Length for PAUSE control
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assign ReservedMulticast = 48'h0180C2000001;
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assign TypeLength = 16'h8808;
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// Address Detection (Multicast or unicast)
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always @ (posedge MRxClk or posedge RxReset)
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begin
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if(RxReset)
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AddressOK <= 1'b0;
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else
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if(DetectionWindow & ByteCntEq0)
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AddressOK <= RxData[7:0] == ReservedMulticast[47:40] | RxData[7:0] == MAC[47:40];
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else
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if(DetectionWindow & ByteCntEq1)
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AddressOK <= (RxData[7:0] == ReservedMulticast[39:32] | RxData[7:0] == MAC[39:32]) & AddressOK;
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else
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if(DetectionWindow & ByteCntEq2)
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AddressOK <= (RxData[7:0] == ReservedMulticast[31:24] | RxData[7:0] == MAC[31:24]) & AddressOK;
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else
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if(DetectionWindow & ByteCntEq3)
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AddressOK <= (RxData[7:0] == ReservedMulticast[23:16] | RxData[7:0] == MAC[23:16]) & AddressOK;
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else
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if(DetectionWindow & ByteCntEq4)
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AddressOK <= (RxData[7:0] == ReservedMulticast[15:8] | RxData[7:0] == MAC[15:8]) & AddressOK;
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else
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if(DetectionWindow & ByteCntEq5)
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AddressOK <= (RxData[7:0] == ReservedMulticast[7:0] | RxData[7:0] == MAC[7:0]) & AddressOK;
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else
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if(ReceiveEnd)
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AddressOK <= 1'b0;
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end
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// TypeLengthOK (Type/Length Control frame detected)
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always @ (posedge MRxClk or posedge RxReset )
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begin
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if(RxReset)
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TypeLengthOK <= 1'b0;
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else
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if(DetectionWindow & ByteCntEq12)
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TypeLengthOK <= ByteCntEq12 & (RxData[7:0] == TypeLength[15:8]);
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else
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if(DetectionWindow & ByteCntEq13)
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TypeLengthOK <= ByteCntEq13 & (RxData[7:0] == TypeLength[7:0]) & TypeLengthOK;
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else
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if(ReceiveEnd)
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TypeLengthOK <= 1'b0;
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end
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// Latch Control Frame Opcode
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always @ (posedge MRxClk or posedge RxReset )
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begin
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if(RxReset)
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OpCodeOK <= 1'b0;
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else
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if(ByteCntEq16)
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OpCodeOK <= 1'b0;
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else
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begin
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if(DetectionWindow & ByteCntEq14)
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OpCodeOK <= ByteCntEq14 & RxData[7:0] == 8'h00;
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if(DetectionWindow & ByteCntEq15)
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OpCodeOK <= ByteCntEq15 & RxData[7:0] == 8'h01 & OpCodeOK;
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end
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end
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// ReceivedPauseFrmWAddr (+Address Check)
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always @ (posedge MRxClk or posedge RxReset )
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begin
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if(RxReset)
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ReceivedPauseFrmWAddr <= 1'b0;
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else
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if(ReceiveEnd)
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ReceivedPauseFrmWAddr <= 1'b0;
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else
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if(ByteCntEq16 & TypeLengthOK & OpCodeOK & AddressOK)
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ReceivedPauseFrmWAddr <= 1'b1;
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end
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// Assembling 16-bit timer value from two 8-bit data
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always @ (posedge MRxClk or posedge RxReset )
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begin
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if(RxReset)
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AssembledTimerValue[15:0] <= 16'h0;
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else
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if(RxStartFrm)
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AssembledTimerValue[15:0] <= 16'h0;
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else
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begin
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if(DetectionWindow & ByteCntEq16)
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AssembledTimerValue[15:8] <= RxData[7:0];
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if(DetectionWindow & ByteCntEq17)
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AssembledTimerValue[7:0] <= RxData[7:0];
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end
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end
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// Detection window (while PAUSE detection is possible)
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always @ (posedge MRxClk or posedge RxReset )
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begin
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if(RxReset)
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DetectionWindow <= 1'b1;
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else
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if(ByteCntEq18)
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DetectionWindow <= 1'b0;
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else
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if(ReceiveEnd)
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DetectionWindow <= 1'b1;
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end
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// Latching Timer Value
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always @ (posedge MRxClk or posedge RxReset )
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begin
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if(RxReset)
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LatchedTimerValue[15:0] <= 16'h0;
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else
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if(DetectionWindow & ReceivedPauseFrmWAddr & ByteCntEq18)
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LatchedTimerValue[15:0] <= AssembledTimerValue[15:0];
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else
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if(ReceiveEnd)
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LatchedTimerValue[15:0] <= 16'h0;
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end
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// Delayed CEC counter
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always @ (posedge MRxClk or posedge RxReset)
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begin
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if(RxReset)
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DlyCrcCnt <= 3'h0;
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else
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if(RxValid & RxEndFrm)
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DlyCrcCnt <= 3'h0;
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else
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if(RxValid & ~RxEndFrm & ~DlyCrcCnt[2])
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DlyCrcCnt <= DlyCrcCnt + 1'b1;
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end
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assign ResetByteCnt = RxEndFrm;
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assign IncrementByteCnt = RxValid & DetectionWindow & ~ByteCntEq18 & (~DlyCrcEn | DlyCrcEn & DlyCrcCnt[2]);
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// Byte counter
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always @ (posedge MRxClk or posedge RxReset)
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begin
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if(RxReset)
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ByteCnt[4:0] <= 5'h0;
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else
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if(ResetByteCnt)
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ByteCnt[4:0] <= 5'h0;
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else
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if(IncrementByteCnt)
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ByteCnt[4:0] <= ByteCnt[4:0] + 1'b1;
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end
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assign ByteCntEq0 = RxValid & ByteCnt[4:0] == 5'h0;
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assign ByteCntEq1 = RxValid & ByteCnt[4:0] == 5'h1;
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assign ByteCntEq2 = RxValid & ByteCnt[4:0] == 5'h2;
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assign ByteCntEq3 = RxValid & ByteCnt[4:0] == 5'h3;
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assign ByteCntEq4 = RxValid & ByteCnt[4:0] == 5'h4;
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assign ByteCntEq5 = RxValid & ByteCnt[4:0] == 5'h5;
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assign ByteCntEq12 = RxValid & ByteCnt[4:0] == 5'h0C;
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assign ByteCntEq13 = RxValid & ByteCnt[4:0] == 5'h0D;
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assign ByteCntEq14 = RxValid & ByteCnt[4:0] == 5'h0E;
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assign ByteCntEq15 = RxValid & ByteCnt[4:0] == 5'h0F;
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assign ByteCntEq16 = RxValid & ByteCnt[4:0] == 5'h10;
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assign ByteCntEq17 = RxValid & ByteCnt[4:0] == 5'h11;
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assign ByteCntEq18 = RxValid & ByteCnt[4:0] == 5'h12 & DetectionWindow;
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assign SetPauseTimer = ReceiveEnd & ReceivedPauseFrmWAddr & ReceivedPacketGood & ReceivedLengthOK & RxFlow;
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assign DecrementPauseTimer = SlotFinished & |PauseTimer;
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// PauseTimer[15:0]
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always @ (posedge MRxClk or posedge RxReset)
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begin
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if(RxReset)
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PauseTimer[15:0] <= 16'h0;
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else
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if(SetPauseTimer)
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PauseTimer[15:0] <= LatchedTimerValue[15:0];
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else
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if(DecrementPauseTimer)
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PauseTimer[15:0] <= PauseTimer[15:0] - 1'b1;
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end
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assign PauseTimerEq0 = ~(|PauseTimer[15:0]);
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// Synchronization of the pause timer
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always @ (posedge MTxClk or posedge TxReset)
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begin
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if(TxReset)
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begin
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PauseTimerEq0_sync1 <= 1'b1;
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PauseTimerEq0_sync2 <= 1'b1;
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end
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else
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begin
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PauseTimerEq0_sync1 <= PauseTimerEq0;
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PauseTimerEq0_sync2 <= PauseTimerEq0_sync1;
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end
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end
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// Pause signal generation
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always @ (posedge MTxClk or posedge TxReset)
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begin
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if(TxReset)
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Pause <= 1'b0;
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else
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if((TxDoneIn | TxAbortIn | ~TxUsedDataOutDetected) & ~TxStartFrmOut)
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Pause <= RxFlow & ~PauseTimerEq0_sync2;
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end
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// Divider2 is used for incrementing the Slot timer every other clock
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always @ (posedge MRxClk or posedge RxReset)
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begin
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if(RxReset)
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Divider2 <= 1'b0;
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else
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if(|PauseTimer[15:0] & RxFlow)
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Divider2 <= ~Divider2;
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else
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Divider2 <= 1'b0;
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end
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assign ResetSlotTimer = RxReset;
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assign IncrementSlotTimer = Pause & RxFlow & Divider2;
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// SlotTimer
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always @ (posedge MRxClk or posedge RxReset)
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begin
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if(RxReset)
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SlotTimer[5:0] <= 6'h0;
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else
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if(ResetSlotTimer)
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SlotTimer[5:0] <= 6'h0;
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else
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if(IncrementSlotTimer)
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SlotTimer[5:0] <= SlotTimer[5:0] + 1'b1;
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end
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assign SlotFinished = &SlotTimer[5:0] & IncrementSlotTimer; // Slot is 512 bits (64 bytes)
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// Pause Frame received
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always @ (posedge MRxClk or posedge RxReset)
|
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begin
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if(RxReset)
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ReceivedPauseFrm <= 1'b0;
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else
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if(RxStatusWriteLatched_sync2 & r_PassAll | ReceivedPauseFrm & (~r_PassAll))
|
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ReceivedPauseFrm <= 1'b0;
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else
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if(ByteCntEq16 & TypeLengthOK & OpCodeOK)
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ReceivedPauseFrm <= 1'b1;
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end
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endmodule
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