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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [ethmac/] [eth_receivecontrol.v] - Diff between revs 409 and 439

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Rev 409	Rev 439
Line 299...	Line 299...
`else`	`else`
`if(RxValid & RxEndFrm)`	`if(RxValid & RxEndFrm)`
`DlyCrcCnt <= 3'h0;`	`DlyCrcCnt <= 3'h0;`
`else`	`else`
`if(RxValid & ~RxEndFrm & ~DlyCrcCnt[2])`	`if(RxValid & ~RxEndFrm & ~DlyCrcCnt[2])`
`DlyCrcCnt <= DlyCrcCnt + 1'b1;`	`DlyCrcCnt <= DlyCrcCnt + 3'd1;`
`end`	`end`


`assign ResetByteCnt = RxEndFrm;`	`assign ResetByteCnt = RxEndFrm;`
`assign IncrementByteCnt = RxValid & DetectionWindow & ~ByteCntEq18 & (~DlyCrcEn \| DlyCrcEn & DlyCrcCnt[2]);`	`assign IncrementByteCnt = RxValid & DetectionWindow & ~ByteCntEq18 &`
	`(~DlyCrcEn \| DlyCrcEn & DlyCrcCnt[2]);`


`// Byte counter`	`// Byte counter`
`always @ (posedge MRxClk or posedge RxReset)`	`always @ (posedge MRxClk or posedge RxReset)`
`begin`	`begin`
Line 317...	Line 318...
`else`	`else`
`if(ResetByteCnt)`	`if(ResetByteCnt)`
`ByteCnt[4:0] <= 5'h0;`	`ByteCnt[4:0] <= 5'h0;`
`else`	`else`
`if(IncrementByteCnt)`	`if(IncrementByteCnt)`
`ByteCnt[4:0] <= ByteCnt[4:0] + 1'b1;`	`ByteCnt[4:0] <= ByteCnt[4:0] + 5'd1;`
`end`	`end`


`assign ByteCntEq0 = RxValid & ByteCnt[4:0] == 5'h0;`	`assign ByteCntEq0 = RxValid & ByteCnt[4:0] == 5'h0;`
`assign ByteCntEq1 = RxValid & ByteCnt[4:0] == 5'h1;`	`assign ByteCntEq1 = RxValid & ByteCnt[4:0] == 5'h1;`
Line 350...	Line 351...
`else`	`else`
`if(SetPauseTimer)`	`if(SetPauseTimer)`
`PauseTimer[15:0] <= LatchedTimerValue[15:0];`	`PauseTimer[15:0] <= LatchedTimerValue[15:0];`
`else`	`else`
`if(DecrementPauseTimer)`	`if(DecrementPauseTimer)`
`PauseTimer[15:0] <= PauseTimer[15:0] - 1'b1;`	`PauseTimer[15:0] <= PauseTimer[15:0] - 16'd1;`
`end`	`end`

`assign PauseTimerEq0 = ~(\|PauseTimer[15:0]);`	`assign PauseTimerEq0 = ~(\|PauseTimer[15:0]);`


Line 411...	Line 412...
`else`	`else`
`if(ResetSlotTimer)`	`if(ResetSlotTimer)`
`SlotTimer[5:0] <= 6'h0;`	`SlotTimer[5:0] <= 6'h0;`
`else`	`else`
`if(IncrementSlotTimer)`	`if(IncrementSlotTimer)`
`SlotTimer[5:0] <= SlotTimer[5:0] + 1'b1;`	`SlotTimer[5:0] <= SlotTimer[5:0] + 6'd1;`
`end`	`end`


`assign SlotFinished = &SlotTimer[5:0] & IncrementSlotTimer; // Slot is 512 bits (64 bytes)`	`assign SlotFinished = &SlotTimer[5:0] & IncrementSlotTimer; // Slot is 512 bits (64 bytes)`

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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [ethmac/] [eth_receivecontrol.v] - Diff between revs 409 and 439