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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [ethmac/] [eth_registers.v] - Diff between revs 409 and 439

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Rev 409 Rev 439
Line 857... Line 857...
         )
         )
begin
begin
  if(Read)  // read
  if(Read)  // read
    begin
    begin
      case(Address)
      case(Address)
        `ETH_MODER_ADR        :  DataOut<=MODEROut;
        `ETH_MODER_ADR        :  DataOut=MODEROut;
        `ETH_INT_SOURCE_ADR   :  DataOut<=INT_SOURCEOut;
        `ETH_INT_SOURCE_ADR   :  DataOut=INT_SOURCEOut;
        `ETH_INT_MASK_ADR     :  DataOut<=INT_MASKOut;
        `ETH_INT_MASK_ADR     :  DataOut=INT_MASKOut;
        `ETH_IPGT_ADR         :  DataOut<=IPGTOut;
        `ETH_IPGT_ADR         :  DataOut=IPGTOut;
        `ETH_IPGR1_ADR        :  DataOut<=IPGR1Out;
        `ETH_IPGR1_ADR        :  DataOut=IPGR1Out;
        `ETH_IPGR2_ADR        :  DataOut<=IPGR2Out;
        `ETH_IPGR2_ADR        :  DataOut=IPGR2Out;
        `ETH_PACKETLEN_ADR    :  DataOut<=PACKETLENOut;
        `ETH_PACKETLEN_ADR    :  DataOut=PACKETLENOut;
        `ETH_COLLCONF_ADR     :  DataOut<=COLLCONFOut;
        `ETH_COLLCONF_ADR     :  DataOut=COLLCONFOut;
        `ETH_CTRLMODER_ADR    :  DataOut<=CTRLMODEROut;
        `ETH_CTRLMODER_ADR    :  DataOut=CTRLMODEROut;
        `ETH_MIIMODER_ADR     :  DataOut<=MIIMODEROut;
        `ETH_MIIMODER_ADR     :  DataOut=MIIMODEROut;
        `ETH_MIICOMMAND_ADR   :  DataOut<=MIICOMMANDOut;
        `ETH_MIICOMMAND_ADR   :  DataOut=MIICOMMANDOut;
        `ETH_MIIADDRESS_ADR   :  DataOut<=MIIADDRESSOut;
        `ETH_MIIADDRESS_ADR   :  DataOut=MIIADDRESSOut;
        `ETH_MIITX_DATA_ADR   :  DataOut<=MIITX_DATAOut;
        `ETH_MIITX_DATA_ADR   :  DataOut=MIITX_DATAOut;
        `ETH_MIIRX_DATA_ADR   :  DataOut<=MIIRX_DATAOut;
        `ETH_MIIRX_DATA_ADR   :  DataOut=MIIRX_DATAOut;
        `ETH_MIISTATUS_ADR    :  DataOut<=MIISTATUSOut;
        `ETH_MIISTATUS_ADR    :  DataOut=MIISTATUSOut;
        `ETH_MAC_ADDR0_ADR    :  DataOut<=MAC_ADDR0Out;
        `ETH_MAC_ADDR0_ADR    :  DataOut=MAC_ADDR0Out;
        `ETH_MAC_ADDR1_ADR    :  DataOut<=MAC_ADDR1Out;
        `ETH_MAC_ADDR1_ADR    :  DataOut=MAC_ADDR1Out;
        `ETH_TX_BD_NUM_ADR    :  DataOut<=TX_BD_NUMOut;
        `ETH_TX_BD_NUM_ADR    :  DataOut=TX_BD_NUMOut;
        `ETH_HASH0_ADR        :  DataOut<=HASH0Out;
        `ETH_HASH0_ADR        :  DataOut=HASH0Out;
        `ETH_HASH1_ADR        :  DataOut<=HASH1Out;
        `ETH_HASH1_ADR        :  DataOut=HASH1Out;
        `ETH_TX_CTRL_ADR      :  DataOut<=TXCTRLOut;
        `ETH_TX_CTRL_ADR      :  DataOut=TXCTRLOut;
        `ETH_DBG_ADR          :  DataOut<=dbg_dat; // debug data out -- JB
        `ETH_DBG_ADR          :  DataOut=dbg_dat; // debug data out -- JB
        default:             DataOut<=32'h0;
        default:             DataOut=32'h0;
      endcase
      endcase
    end
    end
  else
  else
    DataOut<=32'h0;
    DataOut=32'h0;
end
end
 
 
 
 
assign r_RecSmall         = MODEROut[16];
assign r_RecSmall         = MODEROut[16];
assign r_Pad              = MODEROut[15];
assign r_Pad              = MODEROut[15];
assign r_HugEn            = MODEROut[14];
assign r_HugEn            = MODEROut[14];
assign r_CrcEn            = MODEROut[13];
assign r_CrcEn            = MODEROut[13];
assign r_DlyCrcEn         = MODEROut[12];
assign r_DlyCrcEn         = /*MODEROut[12]*/1'b0; // Synthesis bugfix JB
// assign r_Rst           = MODEROut[11];   This signal is not used any more
// assign r_Rst           = MODEROut[11];   This signal is not used any more
assign r_FullD            = MODEROut[10];
assign r_FullD            = MODEROut[10];
assign r_ExDfrEn          = MODEROut[9];
assign r_ExDfrEn          = MODEROut[9];
assign r_NoBckof          = MODEROut[8];
assign r_NoBckof          = MODEROut[8];
assign r_LoopBck          = MODEROut[7];
assign r_LoopBck          = MODEROut[7];

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