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//////////////////////////////////////////////////////////////////////
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//// ////
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//// eth_rxethmac.v ////
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//// ////
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//// This file is part of the Ethernet IP core project ////
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//// http://www.opencores.org/project,ethmac ////
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//// ////
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//// Author(s): ////
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//// - Igor Mohor (igorM@opencores.org) ////
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//// - Novan Hartadi (novan@vlsi.itb.ac.id) ////
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//// - Mahmud Galela (mgalela@vlsi.itb.ac.id) ////
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//// ////
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//// All additional information is avaliable in the Readme.txt ////
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//// file. ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2001 Authors ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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// Revision 1.12 2004/04/26 15:26:23 igorm
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// - Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the
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// previous update of the core.
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// - TxBDAddress is set to 0 after the TX is enabled in the MODER register.
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// - RxBDAddress is set to r_TxBDNum<<1 after the RX is enabled in the MODER
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// register. (thanks to Mathias and Torbjorn)
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// - Multicast reception was fixed. Thanks to Ulrich Gries
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//
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// Revision 1.11 2004/03/17 09:32:15 igorm
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// Multicast detection fixed. Only the LSB of the first byte is checked.
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//
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// Revision 1.10 2002/11/22 01:57:06 mohor
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// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
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// synchronized.
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//
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// Revision 1.9 2002/11/19 17:35:35 mohor
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// AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
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// that a frame was received because of the promiscous mode.
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//
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// Revision 1.8 2002/02/16 07:15:27 mohor
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// Testbench fixed, code simplified, unused signals removed.
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//
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// Revision 1.7 2002/02/15 13:44:28 mohor
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// RxAbort is an output. No need to have is declared as wire.
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//
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// Revision 1.6 2002/02/15 11:17:48 mohor
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// File format changed.
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//
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// Revision 1.5 2002/02/14 20:48:43 billditt
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// Addition of new module eth_addrcheck.v
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//
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// Revision 1.4 2002/01/23 10:28:16 mohor
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// Link in the header changed.
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//
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// Revision 1.3 2001/10/19 08:43:51 mohor
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// eth_timescale.v changed to timescale.v This is done because of the
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// simulation of the few cores in a one joined project.
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//
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// Revision 1.2 2001/09/11 14:17:00 mohor
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// Few little NCSIM warnings fixed.
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//
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// Revision 1.1 2001/08/06 14:44:29 mohor
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// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
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// Include files fixed to contain no path.
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// File names and module names changed ta have a eth_ prologue in the name.
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// File eth_timescale.v is used to define timescale
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// All pin names on the top module are changed to contain _I, _O or _OE at the end.
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// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
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// and Mdo_OE. The bidirectional signal must be created on the top level. This
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// is done due to the ASIC tools.
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//
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// Revision 1.1 2001/07/30 21:23:42 mohor
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// Directory structure changed. Files checked and joind together.
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//
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// Revision 1.1 2001/06/27 21:26:19 mohor
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// Initial release of the RxEthMAC module.
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//
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//
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//
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//
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//
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`include "timescale.v"
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module eth_rxethmac (MRxClk, MRxDV, MRxD, Reset, Transmitting, MaxFL, r_IFG, HugEn, DlyCrcEn,
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RxData, RxValid, RxStartFrm, RxEndFrm, ByteCnt, ByteCntEq0, ByteCntGreat2,
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ByteCntMaxFrame, CrcError, StateIdle, StatePreamble, StateSFD, StateData,
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MAC, r_Pro, r_Bro,r_HASH0, r_HASH1, RxAbort, AddressMiss, PassAll, ControlFrmAddressOK
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);
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parameter Tp = 1;
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input MRxClk;
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input MRxDV;
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input [3:0] MRxD;
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input Transmitting;
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input HugEn;
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input DlyCrcEn;
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input [15:0] MaxFL;
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input r_IFG;
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input Reset;
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input [47:0] MAC; // Station Address
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input r_Bro; // broadcast disable
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input r_Pro; // promiscuous enable
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input [31:0] r_HASH0; // lower 4 bytes Hash Table
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input [31:0] r_HASH1; // upper 4 bytes Hash Table
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input PassAll;
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input ControlFrmAddressOK;
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output [7:0] RxData;
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output RxValid;
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output RxStartFrm;
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output RxEndFrm;
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output [15:0] ByteCnt;
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output ByteCntEq0;
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output ByteCntGreat2;
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output ByteCntMaxFrame;
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output CrcError;
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output StateIdle;
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output StatePreamble;
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output StateSFD;
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output [1:0] StateData;
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output RxAbort;
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output AddressMiss;
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reg [7:0] RxData;
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reg RxValid;
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reg RxStartFrm;
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reg RxEndFrm;
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reg Broadcast;
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reg Multicast;
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reg [5:0] CrcHash;
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reg CrcHashGood;
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reg DelayData;
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reg [7:0] LatchedByte;
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reg [7:0] RxData_d;
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reg RxValid_d;
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reg RxStartFrm_d;
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reg RxEndFrm_d;
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wire MRxDEqD;
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wire MRxDEq5;
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wire StateDrop;
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wire ByteCntEq1;
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wire ByteCntEq2;
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wire ByteCntEq3;
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wire ByteCntEq4;
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wire ByteCntEq5;
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wire ByteCntEq6;
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wire ByteCntEq7;
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wire ByteCntSmall7;
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wire [31:0] Crc;
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wire Enable_Crc;
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wire Initialize_Crc;
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wire [3:0] Data_Crc;
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wire GenerateRxValid;
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wire GenerateRxStartFrm;
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wire GenerateRxEndFrm;
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wire DribbleRxEndFrm;
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wire [3:0] DlyCrcCnt;
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wire IFGCounterEq24;
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assign MRxDEqD = MRxD == 4'hd;
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assign MRxDEq5 = MRxD == 4'h5;
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// Rx State Machine module
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eth_rxstatem rxstatem1 (.MRxClk(MRxClk), .Reset(Reset), .MRxDV(MRxDV), .ByteCntEq0(ByteCntEq0),
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.ByteCntGreat2(ByteCntGreat2), .Transmitting(Transmitting), .MRxDEq5(MRxDEq5),
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.MRxDEqD(MRxDEqD), .IFGCounterEq24(IFGCounterEq24), .ByteCntMaxFrame(ByteCntMaxFrame),
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.StateData(StateData), .StateIdle(StateIdle), .StatePreamble(StatePreamble),
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.StateSFD(StateSFD), .StateDrop(StateDrop)
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);
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// Rx Counters module
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eth_rxcounters rxcounters1 (.MRxClk(MRxClk), .Reset(Reset), .MRxDV(MRxDV), .StateIdle(StateIdle),
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.StateSFD(StateSFD), .StateData(StateData), .StateDrop(StateDrop),
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.StatePreamble(StatePreamble), .MRxDEqD(MRxDEqD), .DlyCrcEn(DlyCrcEn),
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.DlyCrcCnt(DlyCrcCnt), .Transmitting(Transmitting), .MaxFL(MaxFL), .r_IFG(r_IFG),
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.HugEn(HugEn), .IFGCounterEq24(IFGCounterEq24), .ByteCntEq0(ByteCntEq0),
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.ByteCntEq1(ByteCntEq1), .ByteCntEq2(ByteCntEq2), .ByteCntEq3(ByteCntEq3),
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.ByteCntEq4(ByteCntEq4), .ByteCntEq5(ByteCntEq5), .ByteCntEq6(ByteCntEq6),
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.ByteCntEq7(ByteCntEq7), .ByteCntGreat2(ByteCntGreat2),
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.ByteCntSmall7(ByteCntSmall7), .ByteCntMaxFrame(ByteCntMaxFrame),
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.ByteCntOut(ByteCnt)
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);
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// Rx Address Check
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eth_rxaddrcheck rxaddrcheck1
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(.MRxClk(MRxClk), .Reset( Reset), .RxData(RxData),
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.Broadcast (Broadcast), .r_Bro (r_Bro), .r_Pro(r_Pro),
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.ByteCntEq6(ByteCntEq6), .ByteCntEq7(ByteCntEq7), .ByteCntEq2(ByteCntEq2),
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.ByteCntEq3(ByteCntEq3), .ByteCntEq4(ByteCntEq4), .ByteCntEq5(ByteCntEq5),
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.HASH0(r_HASH0), .HASH1(r_HASH1),
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.CrcHash(CrcHash), .CrcHashGood(CrcHashGood), .StateData(StateData),
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.Multicast(Multicast), .MAC(MAC), .RxAbort(RxAbort),
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.RxEndFrm(RxEndFrm), .AddressMiss(AddressMiss), .PassAll(PassAll),
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.ControlFrmAddressOK(ControlFrmAddressOK)
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);
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assign Enable_Crc = MRxDV & (|StateData & ~ByteCntMaxFrame);
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assign Initialize_Crc = StateSFD | DlyCrcEn & (|DlyCrcCnt[3:0]) & DlyCrcCnt[3:0] < 4'h9;
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assign Data_Crc[0] = MRxD[3];
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assign Data_Crc[1] = MRxD[2];
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assign Data_Crc[2] = MRxD[1];
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assign Data_Crc[3] = MRxD[0];
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// Connecting module Crc
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eth_crc crcrx (.Clk(MRxClk), .Reset(Reset), .Data(Data_Crc), .Enable(Enable_Crc), .Initialize(Initialize_Crc),
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.Crc(Crc), .CrcError(CrcError)
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);
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// Latching CRC for use in the hash table
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always @ (posedge MRxClk)
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begin
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CrcHashGood <= StateData[0] & ByteCntEq6;
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end
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always @ (posedge MRxClk)
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begin
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if(Reset | StateIdle)
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CrcHash[5:0] <= 6'h0;
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else
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if(StateData[0] & ByteCntEq6)
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CrcHash[5:0] <= Crc[31:26];
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end
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// Output byte stream
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always @ (posedge MRxClk or posedge Reset)
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begin
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if(Reset)
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begin
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RxData_d[7:0] <= 8'h0;
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DelayData <= 1'b0;
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LatchedByte[7:0] <= 8'h0;
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RxData[7:0] <= 8'h0;
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end
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else
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begin
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LatchedByte[7:0] <= {MRxD[3:0], LatchedByte[7:4]}; // Latched byte
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DelayData <= StateData[0];
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if(GenerateRxValid)
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RxData_d[7:0] <= LatchedByte[7:0] & {8{|StateData}}; // Data goes through only in data state
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else
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if(~DelayData)
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RxData_d[7:0] <= 8'h0; // Delaying data to be valid for two cycles. Zero when not active.
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RxData[7:0] <= RxData_d[7:0]; // Output data byte
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end
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end
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always @ (posedge MRxClk or posedge Reset)
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begin
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if(Reset)
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Broadcast <= 1'b0;
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else
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begin
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if(StateData[0] & ~(&LatchedByte[7:0]) & ByteCntSmall7)
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Broadcast <= 1'b0;
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else
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if(StateData[0] & (&LatchedByte[7:0]) & ByteCntEq1)
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Broadcast <= 1'b1;
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else
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if(RxAbort | RxEndFrm)
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Broadcast <= 1'b0;
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end
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end
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always @ (posedge MRxClk or posedge Reset)
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begin
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if(Reset)
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Multicast <= 1'b0;
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else
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begin
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if(StateData[0] & ByteCntEq1 & LatchedByte[0])
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Multicast <= 1'b1;
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else if(RxAbort | RxEndFrm)
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Multicast <= 1'b0;
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end
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end
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assign GenerateRxValid = StateData[0] & (~ByteCntEq0 | DlyCrcCnt >= 4'h3);
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always @ (posedge MRxClk or posedge Reset)
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begin
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if(Reset)
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begin
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RxValid_d <= 1'b0;
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RxValid <= 1'b0;
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end
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else
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begin
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RxValid_d <= GenerateRxValid;
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RxValid <= RxValid_d;
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end
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end
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assign GenerateRxStartFrm = StateData[0] & (ByteCntEq1 & ~DlyCrcEn | DlyCrcCnt == 4'h3 & DlyCrcEn);
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always @ (posedge MRxClk or posedge Reset)
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begin
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if(Reset)
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begin
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RxStartFrm_d <= 1'b0;
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RxStartFrm <= 1'b0;
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end
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else
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begin
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RxStartFrm_d <= GenerateRxStartFrm;
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RxStartFrm <= RxStartFrm_d;
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end
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end
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assign GenerateRxEndFrm = StateData[0] & (~MRxDV & ByteCntGreat2 | ByteCntMaxFrame);
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assign DribbleRxEndFrm = StateData[1] & ~MRxDV & ByteCntGreat2;
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always @ (posedge MRxClk or posedge Reset)
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begin
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if(Reset)
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begin
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RxEndFrm_d <= 1'b0;
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RxEndFrm <= 1'b0;
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end
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else
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begin
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RxEndFrm_d <= GenerateRxEndFrm;
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RxEndFrm <= RxEndFrm_d | DribbleRxEndFrm;
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end
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end
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endmodule
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