| Line 37... |
Line 37... |
//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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// Revision 1.12 2004/04/26 15:26:23 igorm
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// - Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the
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// previous update of the core.
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// - TxBDAddress is set to 0 after the TX is enabled in the MODER register.
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// - RxBDAddress is set to r_TxBDNum<<1 after the RX is enabled in the MODER
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// register. (thanks to Mathias and Torbjorn)
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// - Multicast reception was fixed. Thanks to Ulrich Gries
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//
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// Revision 1.11 2004/03/17 09:32:15 igorm
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// Multicast detection fixed. Only the LSB of the first byte is checked.
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//
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// Revision 1.10 2002/11/22 01:57:06 mohor
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// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
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// synchronized.
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//
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// Revision 1.9 2002/11/19 17:35:35 mohor
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// AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
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// that a frame was received because of the promiscous mode.
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//
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// Revision 1.8 2002/02/16 07:15:27 mohor
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// Testbench fixed, code simplified, unused signals removed.
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//
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// Revision 1.7 2002/02/15 13:44:28 mohor
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// RxAbort is an output. No need to have is declared as wire.
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//
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// Revision 1.6 2002/02/15 11:17:48 mohor
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// File format changed.
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//
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// Revision 1.5 2002/02/14 20:48:43 billditt
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// Addition of new module eth_addrcheck.v
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//
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// Revision 1.4 2002/01/23 10:28:16 mohor
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// Link in the header changed.
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//
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// Revision 1.3 2001/10/19 08:43:51 mohor
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// eth_timescale.v changed to timescale.v This is done because of the
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// simulation of the few cores in a one joined project.
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//
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// Revision 1.2 2001/09/11 14:17:00 mohor
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// Few little NCSIM warnings fixed.
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//
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// Revision 1.1 2001/08/06 14:44:29 mohor
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// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
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// Include files fixed to contain no path.
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// File names and module names changed ta have a eth_ prologue in the name.
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// File eth_timescale.v is used to define timescale
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// All pin names on the top module are changed to contain _I, _O or _OE at the end.
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// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
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// and Mdo_OE. The bidirectional signal must be created on the top level. This
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// is done due to the ASIC tools.
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//
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// Revision 1.1 2001/07/30 21:23:42 mohor
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// Directory structure changed. Files checked and joind together.
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//
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// Revision 1.1 2001/06/27 21:26:19 mohor
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// Initial release of the RxEthMAC module.
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//
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//
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//
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//
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//
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`include "timescale.v"
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`include "timescale.v"
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module eth_rxethmac (MRxClk, MRxDV, MRxD, Reset, Transmitting, MaxFL, r_IFG, HugEn, DlyCrcEn,
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module eth_rxethmac (MRxClk, MRxDV, MRxD, Reset, Transmitting, MaxFL, r_IFG,
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RxData, RxValid, RxStartFrm, RxEndFrm, ByteCnt, ByteCntEq0, ByteCntGreat2,
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HugEn, DlyCrcEn, RxData, RxValid, RxStartFrm, RxEndFrm,
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ByteCntMaxFrame, CrcError, StateIdle, StatePreamble, StateSFD, StateData,
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ByteCnt, ByteCntEq0, ByteCntGreat2, ByteCntMaxFrame,
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MAC, r_Pro, r_Bro,r_HASH0, r_HASH1, RxAbort, AddressMiss, PassAll, ControlFrmAddressOK
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CrcError, StateIdle, StatePreamble, StateSFD, StateData,
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MAC, r_Pro, r_Bro,r_HASH0, r_HASH1, RxAbort, AddressMiss,
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PassAll, ControlFrmAddressOK
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);
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);
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parameter Tp = 1;
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input MRxClk;
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input MRxClk;
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input MRxDV;
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input MRxDV;
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input [3:0] MRxD;
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input [3:0] MRxD;
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input Transmitting;
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input Transmitting;
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input HugEn;
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input HugEn;
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| Line 191... |
Line 124... |
assign MRxDEqD = MRxD == 4'hd;
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assign MRxDEqD = MRxD == 4'hd;
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assign MRxDEq5 = MRxD == 4'h5;
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assign MRxDEq5 = MRxD == 4'h5;
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// Rx State Machine module
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// Rx State Machine module
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eth_rxstatem rxstatem1 (.MRxClk(MRxClk), .Reset(Reset), .MRxDV(MRxDV), .ByteCntEq0(ByteCntEq0),
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eth_rxstatem rxstatem1
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.ByteCntGreat2(ByteCntGreat2), .Transmitting(Transmitting), .MRxDEq5(MRxDEq5),
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(
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.MRxDEqD(MRxDEqD), .IFGCounterEq24(IFGCounterEq24), .ByteCntMaxFrame(ByteCntMaxFrame),
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.MRxClk(MRxClk),
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.StateData(StateData), .StateIdle(StateIdle), .StatePreamble(StatePreamble),
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.Reset(Reset),
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.StateSFD(StateSFD), .StateDrop(StateDrop)
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.MRxDV(MRxDV),
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.ByteCntEq0(ByteCntEq0),
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.ByteCntGreat2(ByteCntGreat2),
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.Transmitting(Transmitting),
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.MRxDEq5(MRxDEq5),
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.MRxDEqD(MRxDEqD),
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.IFGCounterEq24(IFGCounterEq24),
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.ByteCntMaxFrame(ByteCntMaxFrame),
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.StateData(StateData),
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.StateIdle(StateIdle),
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.StatePreamble(StatePreamble),
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.StateSFD(StateSFD),
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.StateDrop(StateDrop)
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);
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);
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// Rx Counters module
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// Rx Counters module
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eth_rxcounters rxcounters1 (.MRxClk(MRxClk), .Reset(Reset), .MRxDV(MRxDV), .StateIdle(StateIdle),
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eth_rxcounters rxcounters1
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.StateSFD(StateSFD), .StateData(StateData), .StateDrop(StateDrop),
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(.MRxClk(MRxClk),
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.StatePreamble(StatePreamble), .MRxDEqD(MRxDEqD), .DlyCrcEn(DlyCrcEn),
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.Reset(Reset),
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.DlyCrcCnt(DlyCrcCnt), .Transmitting(Transmitting), .MaxFL(MaxFL), .r_IFG(r_IFG),
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.MRxDV(MRxDV),
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.HugEn(HugEn), .IFGCounterEq24(IFGCounterEq24), .ByteCntEq0(ByteCntEq0),
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.StateIdle(StateIdle),
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.ByteCntEq1(ByteCntEq1), .ByteCntEq2(ByteCntEq2), .ByteCntEq3(ByteCntEq3),
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.StateSFD(StateSFD),
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.ByteCntEq4(ByteCntEq4), .ByteCntEq5(ByteCntEq5), .ByteCntEq6(ByteCntEq6),
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.StateData(StateData),
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.ByteCntEq7(ByteCntEq7), .ByteCntGreat2(ByteCntGreat2),
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.StateDrop(StateDrop),
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.ByteCntSmall7(ByteCntSmall7), .ByteCntMaxFrame(ByteCntMaxFrame),
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.StatePreamble(StatePreamble),
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.MRxDEqD(MRxDEqD),
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.DlyCrcEn(DlyCrcEn),
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.DlyCrcCnt(DlyCrcCnt),
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.Transmitting(Transmitting),
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.MaxFL(MaxFL),
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.r_IFG(r_IFG),
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.HugEn(HugEn),
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.IFGCounterEq24(IFGCounterEq24),
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.ByteCntEq0(ByteCntEq0),
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.ByteCntEq1(ByteCntEq1),
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.ByteCntEq2(ByteCntEq2),
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.ByteCntEq3(ByteCntEq3),
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.ByteCntEq4(ByteCntEq4),
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.ByteCntEq5(ByteCntEq5),
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.ByteCntEq6(ByteCntEq6),
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.ByteCntEq7(ByteCntEq7),
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.ByteCntGreat2(ByteCntGreat2),
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.ByteCntSmall7(ByteCntSmall7),
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.ByteCntMaxFrame(ByteCntMaxFrame),
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.ByteCntOut(ByteCnt)
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.ByteCntOut(ByteCnt)
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);
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);
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// Rx Address Check
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// Rx Address Check
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eth_rxaddrcheck rxaddrcheck1
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eth_rxaddrcheck rxaddrcheck1
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(.MRxClk(MRxClk), .Reset( Reset), .RxData(RxData),
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(.MRxClk(MRxClk),
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.Broadcast (Broadcast), .r_Bro (r_Bro), .r_Pro(r_Pro),
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.Reset( Reset),
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.ByteCntEq6(ByteCntEq6), .ByteCntEq7(ByteCntEq7), .ByteCntEq2(ByteCntEq2),
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.RxData(RxData),
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.ByteCntEq3(ByteCntEq3), .ByteCntEq4(ByteCntEq4), .ByteCntEq5(ByteCntEq5),
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.Broadcast (Broadcast),
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.HASH0(r_HASH0), .HASH1(r_HASH1),
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.r_Bro (r_Bro),
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.CrcHash(CrcHash), .CrcHashGood(CrcHashGood), .StateData(StateData),
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.r_Pro(r_Pro),
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.Multicast(Multicast), .MAC(MAC), .RxAbort(RxAbort),
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.ByteCntEq6(ByteCntEq6),
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.RxEndFrm(RxEndFrm), .AddressMiss(AddressMiss), .PassAll(PassAll),
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.ByteCntEq7(ByteCntEq7),
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.ByteCntEq2(ByteCntEq2),
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.ByteCntEq3(ByteCntEq3),
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.ByteCntEq4(ByteCntEq4),
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.ByteCntEq5(ByteCntEq5),
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.HASH0(r_HASH0),
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.HASH1(r_HASH1),
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.CrcHash(CrcHash),
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.CrcHashGood(CrcHashGood),
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.StateData(StateData),
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.Multicast(Multicast),
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.MAC(MAC),
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.RxAbort(RxAbort),
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.RxEndFrm(RxEndFrm),
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.AddressMiss(AddressMiss),
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.PassAll(PassAll),
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.ControlFrmAddressOK(ControlFrmAddressOK)
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.ControlFrmAddressOK(ControlFrmAddressOK)
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);
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);
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assign Enable_Crc = MRxDV & (|StateData & ~ByteCntMaxFrame);
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assign Enable_Crc = MRxDV & (|StateData & ~ByteCntMaxFrame);
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assign Initialize_Crc = StateSFD | DlyCrcEn & (|DlyCrcCnt[3:0]) & DlyCrcCnt[3:0] < 4'h9;
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assign Initialize_Crc = StateSFD | DlyCrcEn & (|DlyCrcCnt[3:0]) &
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DlyCrcCnt[3:0] < 4'h9;
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assign Data_Crc[0] = MRxD[3];
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assign Data_Crc[0] = MRxD[3];
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assign Data_Crc[1] = MRxD[2];
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assign Data_Crc[1] = MRxD[2];
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assign Data_Crc[2] = MRxD[1];
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assign Data_Crc[2] = MRxD[1];
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assign Data_Crc[3] = MRxD[0];
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assign Data_Crc[3] = MRxD[0];
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// Connecting module Crc
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// Connecting module Crc
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eth_crc crcrx (.Clk(MRxClk), .Reset(Reset), .Data(Data_Crc), .Enable(Enable_Crc), .Initialize(Initialize_Crc),
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eth_crc crcrx
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(.Clk(MRxClk),
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.Reset(Reset),
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.Data(Data_Crc),
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.Enable(Enable_Crc),
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.Initialize(Initialize_Crc),
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.Crc(Crc), .CrcError(CrcError)
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.Crc(Crc), .CrcError(CrcError)
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);
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);
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| Line 272... |
Line 257... |
LatchedByte[7:0] <= 8'h0;
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LatchedByte[7:0] <= 8'h0;
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RxData[7:0] <= 8'h0;
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RxData[7:0] <= 8'h0;
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end
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end
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else
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else
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begin
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begin
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LatchedByte[7:0] <= {MRxD[3:0], LatchedByte[7:4]}; // Latched byte
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// Latched byte
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LatchedByte[7:0] <= {MRxD[3:0], LatchedByte[7:4]};
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DelayData <= StateData[0];
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DelayData <= StateData[0];
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if(GenerateRxValid)
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if(GenerateRxValid)
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RxData_d[7:0] <= LatchedByte[7:0] & {8{|StateData}}; // Data goes through only in data state
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// Data goes through only in data state
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RxData_d[7:0] <= LatchedByte[7:0] & {8{|StateData}};
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else
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else
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if(~DelayData)
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if(~DelayData)
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RxData_d[7:0] <= 8'h0; // Delaying data to be valid for two cycles. Zero when not active.
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// Delaying data to be valid for two cycles.
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// Zero when not active.
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RxData_d[7:0] <= 8'h0;
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RxData[7:0] <= RxData_d[7:0]; // Output data byte
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RxData[7:0] <= RxData_d[7:0]; // Output data byte
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end
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end
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end
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end
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| Line 336... |
Line 326... |
RxValid <= RxValid_d;
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RxValid <= RxValid_d;
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end
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end
|
end
|
end
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assign GenerateRxStartFrm = StateData[0] & (ByteCntEq1 & ~DlyCrcEn | DlyCrcCnt == 4'h3 & DlyCrcEn);
|
assign GenerateRxStartFrm = StateData[0] &
|
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((ByteCntEq1 & ~DlyCrcEn) |
|
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((DlyCrcCnt == 4'h3) & DlyCrcEn));
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always @ (posedge MRxClk or posedge Reset)
|
always @ (posedge MRxClk or posedge Reset)
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begin
|
begin
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if(Reset)
|
if(Reset)
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begin
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begin
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| Line 353... |
Line 345... |
RxStartFrm <= RxStartFrm_d;
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RxStartFrm <= RxStartFrm_d;
|
end
|
end
|
end
|
end
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assign GenerateRxEndFrm = StateData[0] & (~MRxDV & ByteCntGreat2 | ByteCntMaxFrame);
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assign GenerateRxEndFrm = StateData[0] &
|
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(~MRxDV & ByteCntGreat2 | ByteCntMaxFrame);
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assign DribbleRxEndFrm = StateData[1] & ~MRxDV & ByteCntGreat2;
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assign DribbleRxEndFrm = StateData[1] & ~MRxDV & ByteCntGreat2;
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|
|
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always @ (posedge MRxClk or posedge Reset)
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always @ (posedge MRxClk or posedge Reset)
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begin
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begin
|
