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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [ethmac/] [eth_shiftreg.v] - Diff between revs 570 and 618

Rev 570	Rev 618
Line 77...	Line 77...

`module eth_shiftreg(Clk, Reset, MdcEn_n, Mdi, Fiad, Rgad, CtrlData, WriteOp, ByteSelect,`	`module eth_shiftreg(Clk, Reset, MdcEn_n, Mdi, Fiad, Rgad, CtrlData, WriteOp, ByteSelect,`
`LatchByte, ShiftedBit, Prsd, LinkFail);`	`LatchByte, ShiftedBit, Prsd, LinkFail);`


`parameter Tp=1;`

`input Clk; // Input clock (Host clock)`	`input Clk; // Input clock (Host clock)`
`input Reset; // Reset signal`	`input Reset; // Reset signal`
`input MdcEn_n; // Enable signal is asserted for one Clk period before Mdc falls.`	`input MdcEn_n; // Enable signal is asserted for one Clk period before Mdc falls.`
`input Mdi; // MII input data`	`input Mdi; // MII input data`
`input [4:0] Fiad; // PHY address`	`input [4:0] Fiad; // PHY address`