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https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk
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module eth_shiftreg(Clk, Reset, MdcEn_n, Mdi, Fiad, Rgad, CtrlData, WriteOp, ByteSelect,
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module eth_shiftreg(Clk, Reset, MdcEn_n, Mdi, Fiad, Rgad, CtrlData, WriteOp, ByteSelect,
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LatchByte, ShiftedBit, Prsd, LinkFail);
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LatchByte, ShiftedBit, Prsd, LinkFail);
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parameter Tp=1;
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input Clk; // Input clock (Host clock)
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input Clk; // Input clock (Host clock)
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input Reset; // Reset signal
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input Reset; // Reset signal
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input MdcEn_n; // Enable signal is asserted for one Clk period before Mdc falls.
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input MdcEn_n; // Enable signal is asserted for one Clk period before Mdc falls.
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input Mdi; // MII input data
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input Mdi; // MII input data
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input [4:0] Fiad; // PHY address
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input [4:0] Fiad; // PHY address
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