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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [ethmac/] [eth_spram_256x32.v] - Diff between revs 409 and 439

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Line 74... Line 74...
`include "ethmac_defines.v"
`include "ethmac_defines.v"
`include "timescale.v"
`include "timescale.v"
 
 
module eth_spram_256x32(
module eth_spram_256x32(
                        // Generic synchronous single-port RAM interface
                        // Generic synchronous single-port RAM interface
                        clk, rst, ce, we, oe, addr, di, do
                        clk, rst, ce, we, oe, addr, di, dato
 
 
`ifdef ETH_BIST
`ifdef ETH_BIST
                        ,
                        ,
                        // debug chain signals
                        // debug chain signals
                        mbist_si_i,       // bist scan serial in
                        mbist_si_i,       // bist scan serial in
Line 99... Line 99...
   input           ce;   // Chip enable input, active high
   input           ce;   // Chip enable input, active high
   input [we_width-1:0] we;   // Write enable input, active high
   input [we_width-1:0] we;   // Write enable input, active high
   input                oe;   // Output enable input, active high
   input                oe;   // Output enable input, active high
   input [7:0]           addr; // address bus inputs
   input [7:0]           addr; // address bus inputs
   input [31:0]  di;   // input data bus
   input [31:0]  di;   // input data bus
   output [31:0]         do;   // output data bus
   output [31:0]         dato;   // output data bus
 
 
 
 
`ifdef ETH_BIST
`ifdef ETH_BIST
   input           mbist_si_i;       // bist scan serial in
   input           mbist_si_i;       // bist scan serial in
   output          mbist_so_o;       // bist scan serial out
   output          mbist_so_o;       // bist scan serial out
Line 134... Line 134...
    .RST     (rst)
    .RST     (rst)
    );*/
    );*/
 
 
   RAMB4_S8 ram0
   RAMB4_S8 ram0
     (
     (
      .DO      (do[7:0]),
      .DO      (dato[7:0]),
      .ADDR    ({1'b0, addr}),
      .ADDR    ({1'b0, addr}),
      .DI      (di[7:0]),
      .DI      (di[7:0]),
      .EN      (ce),
      .EN      (ce),
      .CLK     (clk),
      .CLK     (clk),
      .WE      (we[0]),
      .WE      (we[0]),
      .RST     (rst)
      .RST     (rst)
      );
      );
 
 
   RAMB4_S8 ram1
   RAMB4_S8 ram1
     (
     (
      .DO      (do[15:8]),
      .DO      (dato[15:8]),
      .ADDR    ({1'b0, addr}),
      .ADDR    ({1'b0, addr}),
      .DI      (di[15:8]),
      .DI      (di[15:8]),
      .EN      (ce),
      .EN      (ce),
      .CLK     (clk),
      .CLK     (clk),
      .WE      (we[1]),
      .WE      (we[1]),
      .RST     (rst)
      .RST     (rst)
      );
      );
 
 
   RAMB4_S8 ram2
   RAMB4_S8 ram2
     (
     (
      .DO      (do[23:16]),
      .DO      (dato[23:16]),
      .ADDR    ({1'b0, addr}),
      .ADDR    ({1'b0, addr}),
      .DI      (di[23:16]),
      .DI      (di[23:16]),
      .EN      (ce),
      .EN      (ce),
      .CLK     (clk),
      .CLK     (clk),
      .WE      (we[2]),
      .WE      (we[2]),
      .RST     (rst)
      .RST     (rst)
      );
      );
 
 
   RAMB4_S8 ram3
   RAMB4_S8 ram3
     (
     (
      .DO      (do[31:24]),
      .DO      (dato[31:24]),
      .ADDR    ({1'b0, addr}),
      .ADDR    ({1'b0, addr}),
      .DI      (di[31:24]),
      .DI      (di[31:24]),
      .EN      (ce),
      .EN      (ce),
      .CLK     (clk),
      .CLK     (clk),
      .WE      (we[3]),
      .WE      (we[3]),
Line 192... Line 192...
        .CEN        (!ce),
        .CEN        (!ce),
        .WEN        (~we),
        .WEN        (~we),
        .OEN        (!oe),
        .OEN        (!oe),
        .ADR        (addr),
        .ADR        (addr),
        .DI         (di),
        .DI         (di),
        .DOUT       (do)
        .DOUT       (dato)
 
 
  `ifdef ETH_BIST
  `ifdef ETH_BIST
        ,
        ,
        // debug chain signals
        // debug chain signals
        .mbist_si_i       (mbist_si_i),
        .mbist_si_i       (mbist_si_i),
Line 220... Line 220...
        .CEN        (!ce),
        .CEN        (!ce),
        .WEN        (~we),
        .WEN        (~we),
        .OEN        (!oe),
        .OEN        (!oe),
        .A          (addr),
        .A          (addr),
        .D          (di),
        .D          (di),
        .Q          (do)
        .Q          (dato)
 
 
   `ifdef ETH_BIST
   `ifdef ETH_BIST
        ,
        ,
        // debug chain signals
        // debug chain signals
        .mbist_si_i       (mbist_si_i),
        .mbist_si_i       (mbist_si_i),
Line 240... Line 240...
     (
     (
      .address        (addr),
      .address        (addr),
      .wren           (ce & we),
      .wren           (ce & we),
      .clock          (clk),
      .clock          (clk),
      .data           (di),
      .data           (di),
      .q              (do)
      .q              (dato)
      );  //exemplar attribute altera_spram_256x32_inst NOOPT TRUE
      );  //exemplar attribute altera_spram_256x32_inst NOOPT TRUE
 
 
   `else   // !ETH_ALTERA_ALTSYNCRAM
   `else   // !ETH_ALTERA_ALTSYNCRAM
 
 
 
 
Line 266... Line 266...
 
 
   //
   //
   // Data output drivers
   // Data output drivers
   //
   //
   //assign do = (oe & ce) ? q : {32{1'bz}};
   //assign do = (oe & ce) ? q : {32{1'bz}};
   assign do = (oe & ce) ? q : {32{1'bx}};
   assign dato = (oe & ce) ? q : {32{1'bx}};
 
 
   //
   //
   // RAM read and write
   // RAM read and write
   //
   //
 
 
Line 319... Line 319...
   task print_ram;
   task print_ram;
      input [7:0] start;
      input [7:0] start;
      input [7:0] finish;
      input [7:0] finish;
      integer     rnum;
      integer     rnum;
      begin
      begin
         for (rnum=start;rnum<=finish;rnum=rnum+1)
         for (rnum={24'd0,start};rnum<={24'd0,finish};rnum=rnum+1)
           $display("Addr %h = %0h %0h %0h %0h",rnum,mem3[rnum],mem2[rnum],mem1[rnum],mem0[rnum]);
           $display("Addr %h = %0h %0h %0h %0h",rnum,mem3[rnum],mem2[rnum],mem1[rnum],mem0[rnum]);
      end
      end
   endtask
   endtask
 
 
   `endif  // !ETH_ALTERA_ALTSYNCRAM
   `endif  // !ETH_ALTERA_ALTSYNCRAM

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