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//////////////////////////////////////////////////////////////////////
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//// ////
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//// eth_txethmac.v ////
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/// ////
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//// This file is part of the Ethernet IP core project ////
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//// http://www.opencores.org/project,ethmac ////
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//// ////
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//// Author(s): ////
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//// - Igor Mohor (igorM@opencores.org) ////
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//// - Novan Hartadi (novan@vlsi.itb.ac.id) ////
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//// - Mahmud Galela (mgalela@vlsi.itb.ac.id) ////
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//// ////
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//// All additional information is avaliable in the Readme.txt ////
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//// file. ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2001 Authors ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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// Revision 1.8 2003/01/30 13:33:24 mohor
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// When padding was enabled and crc disabled, frame was not ended correctly.
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//
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// Revision 1.7 2002/02/26 16:24:01 mohor
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// RetryCntLatched was unused and removed from design
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//
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// Revision 1.6 2002/02/22 12:56:35 mohor
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// Retry is not activated when a Tx Underrun occured
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//
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// Revision 1.5 2002/02/11 09:18:22 mohor
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// Tx status is written back to the BD.
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//
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// Revision 1.4 2002/01/23 10:28:16 mohor
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// Link in the header changed.
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//
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// Revision 1.3 2001/10/19 08:43:51 mohor
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// eth_timescale.v changed to timescale.v This is done because of the
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// simulation of the few cores in a one joined project.
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//
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// Revision 1.2 2001/09/11 14:17:00 mohor
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// Few little NCSIM warnings fixed.
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//
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// Revision 1.1 2001/08/06 14:44:29 mohor
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// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
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// Include files fixed to contain no path.
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// File names and module names changed ta have a eth_ prologue in the name.
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// File eth_timescale.v is used to define timescale
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// All pin names on the top module are changed to contain _I, _O or _OE at the end.
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// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
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// and Mdo_OE. The bidirectional signal must be created on the top level. This
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// is done due to the ASIC tools.
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//
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// Revision 1.1 2001/07/30 21:23:42 mohor
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// Directory structure changed. Files checked and joind together.
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//
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// Revision 1.3 2001/06/19 18:16:40 mohor
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// TxClk changed to MTxClk (as discribed in the documentation).
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// Crc changed so only one file can be used instead of two.
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//
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// Revision 1.2 2001/06/19 10:38:08 mohor
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// Minor changes in header.
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//
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// Revision 1.1 2001/06/19 10:27:58 mohor
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// TxEthMAC initial release.
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//
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//
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//
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`include "timescale.v"
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module eth_txethmac (MTxClk, Reset, TxStartFrm, TxEndFrm, TxUnderRun, TxData, CarrierSense,
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Collision, Pad, CrcEn, FullD, HugEn, DlyCrcEn, MinFL, MaxFL, IPGT,
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IPGR1, IPGR2, CollValid, MaxRet, NoBckof, ExDfrEn,
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MTxD, MTxEn, MTxErr, TxDone, TxRetry, TxAbort, TxUsedData, WillTransmit,
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ResetCollision, RetryCnt, StartTxDone, StartTxAbort, MaxCollisionOccured,
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LateCollision, DeferIndication, StatePreamble, StateData
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);
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parameter Tp = 1;
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input MTxClk; // Transmit clock (from PHY)
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input Reset; // Reset
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input TxStartFrm; // Transmit packet start frame
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input TxEndFrm; // Transmit packet end frame
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input TxUnderRun; // Transmit packet under-run
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input [7:0] TxData; // Transmit packet data byte
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input CarrierSense; // Carrier sense (synchronized)
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input Collision; // Collision (synchronized)
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input Pad; // Pad enable (from register)
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input CrcEn; // Crc enable (from register)
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input FullD; // Full duplex (from register)
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input HugEn; // Huge packets enable (from register)
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input DlyCrcEn; // Delayed Crc enabled (from register)
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input [15:0] MinFL; // Minimum frame length (from register)
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input [15:0] MaxFL; // Maximum frame length (from register)
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input [6:0] IPGT; // Back to back transmit inter packet gap parameter (from register)
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input [6:0] IPGR1; // Non back to back transmit inter packet gap parameter IPGR1 (from register)
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input [6:0] IPGR2; // Non back to back transmit inter packet gap parameter IPGR2 (from register)
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input [5:0] CollValid; // Valid collision window (from register)
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input [3:0] MaxRet; // Maximum retry number (from register)
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input NoBckof; // No backoff (from register)
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input ExDfrEn; // Excessive defferal enable (from register)
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output [3:0] MTxD; // Transmit nibble (to PHY)
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output MTxEn; // Transmit enable (to PHY)
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output MTxErr; // Transmit error (to PHY)
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output TxDone; // Transmit packet done (to RISC)
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output TxRetry; // Transmit packet retry (to RISC)
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output TxAbort; // Transmit packet abort (to RISC)
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output TxUsedData; // Transmit packet used data (to RISC)
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output WillTransmit; // Will transmit (to RxEthMAC)
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output ResetCollision; // Reset Collision (for synchronizing collision)
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output [3:0] RetryCnt; // Latched Retry Counter for tx status purposes
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output StartTxDone;
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output StartTxAbort;
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output MaxCollisionOccured;
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output LateCollision;
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output DeferIndication;
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output StatePreamble;
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output [1:0] StateData;
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reg [3:0] MTxD;
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reg MTxEn;
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reg MTxErr;
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reg TxDone;
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reg TxRetry;
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reg TxAbort;
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reg TxUsedData;
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reg WillTransmit;
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reg ColWindow;
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reg StopExcessiveDeferOccured;
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reg [3:0] RetryCnt;
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reg [3:0] MTxD_d;
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reg StatusLatch;
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reg PacketFinished_q;
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reg PacketFinished;
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wire ExcessiveDeferOccured;
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wire StartIPG;
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wire StartPreamble;
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wire [1:0] StartData;
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wire StartFCS;
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wire StartJam;
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wire StartDefer;
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wire StartBackoff;
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wire StateDefer;
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wire StateIPG;
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wire StateIdle;
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wire StatePAD;
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wire StateFCS;
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wire StateJam;
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wire StateJam_q;
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wire StateBackOff;
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wire StateSFD;
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wire StartTxRetry;
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wire UnderRun;
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wire TooBig;
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wire [31:0] Crc;
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wire CrcError;
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wire [2:0] DlyCrcCnt;
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wire [15:0] NibCnt;
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wire NibCntEq7;
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wire NibCntEq15;
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wire NibbleMinFl;
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wire ExcessiveDefer;
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wire [15:0] ByteCnt;
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wire MaxFrame;
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wire RetryMax;
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wire RandomEq0;
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wire RandomEqByteCnt;
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wire PacketFinished_d;
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assign ResetCollision = ~(StatePreamble | (|StateData) | StatePAD | StateFCS);
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assign ExcessiveDeferOccured = TxStartFrm & StateDefer & ExcessiveDefer & ~StopExcessiveDeferOccured;
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assign StartTxDone = ~Collision & (StateFCS & NibCntEq7 | StateData[1] & TxEndFrm & (~Pad | Pad & NibbleMinFl) & ~CrcEn);
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assign UnderRun = StateData[0] & TxUnderRun & ~Collision;
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assign TooBig = ~Collision & MaxFrame & (StateData[0] & ~TxUnderRun | StateFCS);
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// assign StartTxRetry = StartJam & (ColWindow & ~RetryMax);
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assign StartTxRetry = StartJam & (ColWindow & ~RetryMax) & ~UnderRun;
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assign LateCollision = StartJam & ~ColWindow & ~UnderRun;
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assign MaxCollisionOccured = StartJam & ColWindow & RetryMax;
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assign StateSFD = StatePreamble & NibCntEq15;
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assign StartTxAbort = TooBig | UnderRun | ExcessiveDeferOccured | LateCollision | MaxCollisionOccured;
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// StopExcessiveDeferOccured
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always @ (posedge MTxClk or posedge Reset)
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begin
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if(Reset)
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StopExcessiveDeferOccured <= 1'b0;
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else
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begin
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if(~TxStartFrm)
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StopExcessiveDeferOccured <= 1'b0;
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else
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if(ExcessiveDeferOccured)
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StopExcessiveDeferOccured <= 1'b1;
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end
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end
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// Collision Window
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always @ (posedge MTxClk or posedge Reset)
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begin
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if(Reset)
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ColWindow <= 1'b1;
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else
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begin
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if(~Collision & ByteCnt[5:0] == CollValid[5:0] & (StateData[1] | StatePAD & NibCnt[0] | StateFCS & NibCnt[0]))
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ColWindow <= 1'b0;
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else
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if(StateIdle | StateIPG)
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ColWindow <= 1'b1;
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end
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end
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// Start Window
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always @ (posedge MTxClk or posedge Reset)
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begin
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if(Reset)
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StatusLatch <= 1'b0;
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else
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begin
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if(~TxStartFrm)
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StatusLatch <= 1'b0;
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else
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if(ExcessiveDeferOccured | StateIdle)
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StatusLatch <= 1'b1;
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end
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end
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// Transmit packet used data
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always @ (posedge MTxClk or posedge Reset)
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begin
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if(Reset)
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TxUsedData <= 1'b0;
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else
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TxUsedData <= |StartData;
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end
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// Transmit packet done
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always @ (posedge MTxClk or posedge Reset)
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begin
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if(Reset)
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TxDone <= 1'b0;
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else
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begin
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if(TxStartFrm & ~StatusLatch)
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TxDone <= 1'b0;
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else
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if(StartTxDone)
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TxDone <= 1'b1;
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end
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end
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// Transmit packet retry
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always @ (posedge MTxClk or posedge Reset)
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begin
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if(Reset)
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TxRetry <= 1'b0;
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else
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begin
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if(TxStartFrm & ~StatusLatch)
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TxRetry <= 1'b0;
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else
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if(StartTxRetry)
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TxRetry <= 1'b1;
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end
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end
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// Transmit packet abort
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always @ (posedge MTxClk or posedge Reset)
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begin
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if(Reset)
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TxAbort <= 1'b0;
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else
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begin
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if(TxStartFrm & ~StatusLatch & ~ExcessiveDeferOccured)
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TxAbort <= 1'b0;
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else
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if(StartTxAbort)
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TxAbort <= 1'b1;
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end
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end
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// Retry counter
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always @ (posedge MTxClk or posedge Reset)
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begin
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if(Reset)
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RetryCnt[3:0] <= 4'h0;
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else
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begin
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if(ExcessiveDeferOccured | UnderRun | TooBig | StartTxDone | TxUnderRun
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| StateJam & NibCntEq7 & (~ColWindow | RetryMax))
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RetryCnt[3:0] <= 4'h0;
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else
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if(StateJam & NibCntEq7 & ColWindow & (RandomEq0 | NoBckof) | StateBackOff & RandomEqByteCnt)
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RetryCnt[3:0] <= RetryCnt[3:0] + 1'b1;
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end
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end
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assign RetryMax = RetryCnt[3:0] == MaxRet[3:0];
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// Transmit nibble
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always @ (StatePreamble or StateData or StateData or StateFCS or StateJam or StateSFD or TxData or
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Crc or NibCntEq15)
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begin
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if(StateData[0])
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MTxD_d[3:0] = TxData[3:0]; // Lower nibble
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else
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if(StateData[1])
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MTxD_d[3:0] = TxData[7:4]; // Higher nibble
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else
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if(StateFCS)
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MTxD_d[3:0] = {~Crc[28], ~Crc[29], ~Crc[30], ~Crc[31]}; // Crc
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else
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if(StateJam)
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MTxD_d[3:0] = 4'h9; // Jam pattern
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else
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if(StatePreamble)
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if(NibCntEq15)
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MTxD_d[3:0] = 4'hd; // SFD
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else
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MTxD_d[3:0] = 4'h5; // Preamble
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else
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MTxD_d[3:0] = 4'h0;
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end
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// Transmit Enable
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always @ (posedge MTxClk or posedge Reset)
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begin
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if(Reset)
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MTxEn <= 1'b0;
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else
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MTxEn <= StatePreamble | (|StateData) | StatePAD | StateFCS | StateJam;
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end
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// Transmit nibble
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always @ (posedge MTxClk or posedge Reset)
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begin
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if(Reset)
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MTxD[3:0] <= 4'h0;
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else
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MTxD[3:0] <= MTxD_d[3:0];
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end
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// Transmit error
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always @ (posedge MTxClk or posedge Reset)
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begin
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if(Reset)
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MTxErr <= 1'b0;
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else
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MTxErr <= TooBig | UnderRun;
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end
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// WillTransmit
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always @ (posedge MTxClk or posedge Reset)
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begin
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if(Reset)
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WillTransmit <= 1'b0;
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else
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WillTransmit <= StartPreamble | StatePreamble | (|StateData) | StatePAD | StateFCS | StateJam;
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end
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assign PacketFinished_d = StartTxDone | TooBig | UnderRun | LateCollision | MaxCollisionOccured | ExcessiveDeferOccured;
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// Packet finished
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always @ (posedge MTxClk or posedge Reset)
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begin
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if(Reset)
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begin
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PacketFinished <= 1'b0;
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PacketFinished_q <= 1'b0;
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end
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else
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begin
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PacketFinished <= PacketFinished_d;
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PacketFinished_q <= PacketFinished;
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end
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end
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// Connecting module Counters
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eth_txcounters txcounters1 (.StatePreamble(StatePreamble), .StateIPG(StateIPG), .StateData(StateData),
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.StatePAD(StatePAD), .StateFCS(StateFCS), .StateJam(StateJam), .StateBackOff(StateBackOff),
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.StateDefer(StateDefer), .StateIdle(StateIdle), .StartDefer(StartDefer), .StartIPG(StartIPG),
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.StartFCS(StartFCS), .StartJam(StartJam), .TxStartFrm(TxStartFrm), .MTxClk(MTxClk),
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.Reset(Reset), .MinFL(MinFL), .MaxFL(MaxFL), .HugEn(HugEn), .ExDfrEn(ExDfrEn),
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.PacketFinished_q(PacketFinished_q), .DlyCrcEn(DlyCrcEn), .StartBackoff(StartBackoff),
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.StateSFD(StateSFD), .ByteCnt(ByteCnt), .NibCnt(NibCnt), .ExcessiveDefer(ExcessiveDefer),
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.NibCntEq7(NibCntEq7), .NibCntEq15(NibCntEq15), .MaxFrame(MaxFrame), .NibbleMinFl(NibbleMinFl),
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.DlyCrcCnt(DlyCrcCnt)
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);
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// Connecting module StateM
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eth_txstatem txstatem1 (.MTxClk(MTxClk), .Reset(Reset), .ExcessiveDefer(ExcessiveDefer), .CarrierSense(CarrierSense),
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.NibCnt(NibCnt[6:0]), .IPGT(IPGT), .IPGR1(IPGR1), .IPGR2(IPGR2), .FullD(FullD),
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.TxStartFrm(TxStartFrm), .TxEndFrm(TxEndFrm), .TxUnderRun(TxUnderRun), .Collision(Collision),
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.UnderRun(UnderRun), .StartTxDone(StartTxDone), .TooBig(TooBig), .NibCntEq7(NibCntEq7),
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.NibCntEq15(NibCntEq15), .MaxFrame(MaxFrame), .Pad(Pad), .CrcEn(CrcEn),
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.NibbleMinFl(NibbleMinFl), .RandomEq0(RandomEq0), .ColWindow(ColWindow), .RetryMax(RetryMax),
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.NoBckof(NoBckof), .RandomEqByteCnt(RandomEqByteCnt), .StateIdle(StateIdle),
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.StateIPG(StateIPG), .StatePreamble(StatePreamble), .StateData(StateData), .StatePAD(StatePAD),
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.StateFCS(StateFCS), .StateJam(StateJam), .StateJam_q(StateJam_q), .StateBackOff(StateBackOff),
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.StateDefer(StateDefer), .StartFCS(StartFCS), .StartJam(StartJam), .StartBackoff(StartBackoff),
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.StartDefer(StartDefer), .DeferIndication(DeferIndication), .StartPreamble(StartPreamble), .StartData(StartData), .StartIPG(StartIPG)
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);
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|
|
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wire Enable_Crc;
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wire [3:0] Data_Crc;
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wire Initialize_Crc;
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|
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assign Enable_Crc = ~StateFCS;
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assign Data_Crc[0] = StateData[0]? TxData[3] : StateData[1]? TxData[7] : 1'b0;
|
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assign Data_Crc[1] = StateData[0]? TxData[2] : StateData[1]? TxData[6] : 1'b0;
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assign Data_Crc[2] = StateData[0]? TxData[1] : StateData[1]? TxData[5] : 1'b0;
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assign Data_Crc[3] = StateData[0]? TxData[0] : StateData[1]? TxData[4] : 1'b0;
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assign Initialize_Crc = StateIdle | StatePreamble | (|DlyCrcCnt);
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// Connecting module Crc
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eth_crc txcrc (.Clk(MTxClk), .Reset(Reset), .Data(Data_Crc), .Enable(Enable_Crc), .Initialize(Initialize_Crc),
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.Crc(Crc), .CrcError(CrcError)
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);
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// Connecting module Random
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eth_random random1 (.MTxClk(MTxClk), .Reset(Reset), .StateJam(StateJam), .StateJam_q(StateJam_q), .RetryCnt(RetryCnt),
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.NibCnt(NibCnt), .ByteCnt(ByteCnt[9:0]), .RandomEq0(RandomEq0), .RandomEqByteCnt(RandomEqByteCnt));
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endmodule
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