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//////////////////////////////////////////////////////////////////////
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//// ////
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//// eth_wishbone.v ////
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//// ////
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//// This file is part of the Ethernet IP core project ////
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//// http://www.opencores.org/project,ethmac ////
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//// ////
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//// Author(s): ////
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//// - Igor Mohor (igorM@opencores.org) ////
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//// ////
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//// All additional information is available in the Readme.txt ////
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//// file. ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2001, 2002 Authors ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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`include "ethmac_defines.v"
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`include "timescale.v"
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module eth_wishbone
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(
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// WISHBONE common
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WB_CLK_I, WB_DAT_I, WB_DAT_O,
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// WISHBONE slave
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WB_ADR_I, WB_WE_I, WB_ACK_O,
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BDCs,
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Reset,
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// WISHBONE master
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m_wb_adr_o, m_wb_sel_o, m_wb_we_o,
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m_wb_dat_o, m_wb_dat_i, m_wb_cyc_o,
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m_wb_stb_o, m_wb_ack_i, m_wb_err_i,
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`ifdef ETH_WISHBONE_B3
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m_wb_cti_o, m_wb_bte_o,
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`endif
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//TX
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MTxClk, TxStartFrm, TxEndFrm, TxUsedData, TxData,
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TxRetry, TxAbort, TxUnderRun, TxDone, PerPacketCrcEn,
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PerPacketPad,
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//RX
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MRxClk, RxData, RxValid, RxStartFrm, RxEndFrm, RxAbort, RxStatusWriteLatched_sync2,
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// Register
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r_TxEn, r_RxEn, r_TxBDNum, r_RxFlow, r_PassAll,
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// Interrupts
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TxB_IRQ, TxE_IRQ, RxB_IRQ, RxE_IRQ, Busy_IRQ,
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// Rx Status
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InvalidSymbol, LatchedCrcError, RxLateCollision, ShortFrame, DribbleNibble,
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ReceivedPacketTooBig, RxLength, LoadRxStatus, ReceivedPacketGood, AddressMiss,
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ReceivedPauseFrm,
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// Tx Status
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RetryCntLatched, RetryLimit, LateCollLatched, DeferLatched, RstDeferLatched, CarrierSenseLost
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// Bist
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`ifdef ETH_BIST
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,
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// debug chain signals
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mbist_si_i, // bist scan serial in
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mbist_so_o, // bist scan serial out
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mbist_ctrl_i // bist chain shift control
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`endif
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`ifdef WISHBONE_DEBUG
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,
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dbg_dat0
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`endif
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);
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//parameter Tp = 1;
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parameter Tp = 0;
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// WISHBONE common
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input WB_CLK_I; // WISHBONE clock
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input [31:0] WB_DAT_I; // WISHBONE data input
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output [31:0] WB_DAT_O; // WISHBONE data output
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// WISHBONE slave
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input [9:2] WB_ADR_I; // WISHBONE address input
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input WB_WE_I; // WISHBONE write enable input
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input [3:0] BDCs; // Buffer descriptors are selected
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output WB_ACK_O; // WISHBONE acknowledge output
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// WISHBONE master
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output [29:0] m_wb_adr_o; //
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output [3:0] m_wb_sel_o; //
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output m_wb_we_o; //
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output [31:0] m_wb_dat_o; //
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output m_wb_cyc_o; //
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output m_wb_stb_o; //
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input [31:0] m_wb_dat_i; //
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input m_wb_ack_i; //
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input m_wb_err_i; //
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`ifdef ETH_WISHBONE_B3
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output [2:0] m_wb_cti_o; // Cycle Type Identifier
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`ifdef BURST_4BEAT
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output reg [1:0] m_wb_bte_o; // Burst Type Extension
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`else
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output [1:0] m_wb_bte_o; // Burst Type Extension
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`endif
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reg [2:0] m_wb_cti_o; // Cycle Type Identifier
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`endif
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input Reset; // Reset signal
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// Rx Status signals
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input InvalidSymbol; // Invalid symbol was received during
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// reception in 100 Mbps mode
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input LatchedCrcError; // CRC error
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input RxLateCollision; // Late collision occured while receiving
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// frame
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input ShortFrame; // Frame shorter then the minimum size
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// (r_MinFL) was received while small
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// packets are enabled (r_RecSmall)
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input DribbleNibble; // Extra nibble received
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input ReceivedPacketTooBig;// Received packet is bigger than
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// r_MaxFL
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input [15:0] RxLength; // Length of the incoming frame
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input LoadRxStatus; // Rx status was loaded
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input ReceivedPacketGood;// Received packet's length and CRC are
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// good
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input AddressMiss; // When a packet is received AddressMiss
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// status is written to the Rx BD
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input r_RxFlow;
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input r_PassAll;
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input ReceivedPauseFrm;
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// Tx Status signals
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input [3:0] RetryCntLatched; // Latched Retry Counter
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input RetryLimit; // Retry limit reached (Retry Max value +
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// 1 attempts were made)
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input LateCollLatched; // Late collision occured
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input DeferLatched; // Defer indication (Frame was defered
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// before sucessfully sent)
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output RstDeferLatched;
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input CarrierSenseLost; // Carrier Sense was lost during the
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// frame transmission
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// Tx
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input MTxClk; // Transmit clock (from PHY)
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input TxUsedData; // Transmit packet used data
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input TxRetry; // Transmit packet retry
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input TxAbort; // Transmit packet abort
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input TxDone; // Transmission ended
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output TxStartFrm; // Transmit packet start frame
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output TxEndFrm; // Transmit packet end frame
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output [7:0] TxData; // Transmit packet data byte
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output TxUnderRun; // Transmit packet under-run
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output PerPacketCrcEn; // Per packet crc enable
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output PerPacketPad; // Per packet pading
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// Rx
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input MRxClk; // Receive clock (from PHY)
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input [7:0] RxData; // Received data byte (from PHY)
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input RxValid; //
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input RxStartFrm; //
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input RxEndFrm; //
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input RxAbort; // This signal is set when address doesn't
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// match.
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output RxStatusWriteLatched_sync2;
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//Register
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input r_TxEn; // Transmit enable
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input r_RxEn; // Receive enable
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input [7:0] r_TxBDNum; // Receive buffer descriptor number
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// Interrupts
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output TxB_IRQ;
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output TxE_IRQ;
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output RxB_IRQ;
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output RxE_IRQ;
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output Busy_IRQ;
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// Bist
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`ifdef ETH_BIST
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input mbist_si_i; // bist scan serial in
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output mbist_so_o; // bist scan serial out
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input [`ETH_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
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`endif
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`ifdef WISHBONE_DEBUG
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output [31:0] dbg_dat0;
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`endif
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reg TxB_IRQ;
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reg TxE_IRQ;
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reg RxB_IRQ;
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reg RxE_IRQ;
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reg TxStartFrm;
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reg TxEndFrm;
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reg [7:0] TxData;
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reg TxUnderRun;
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reg TxUnderRun_wb;
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reg TxBDRead;
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wire TxStatusWrite;
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reg [1:0] TxValidBytesLatched;
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reg [15:0] TxLength;
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reg [15:0] LatchedTxLength;
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reg [14:11] TxStatus;
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reg [14:13] RxStatus;
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reg TxStartFrm_wb;
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reg TxRetry_wb;
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reg TxAbort_wb;
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reg TxDone_wb;
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reg TxDone_wb_q;
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reg TxAbort_wb_q;
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reg TxRetry_wb_q;
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reg TxRetryPacket;
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reg TxRetryPacket_NotCleared;
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reg TxDonePacket;
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reg TxDonePacket_NotCleared;
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reg TxAbortPacket;
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reg TxAbortPacket_NotCleared;
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reg RxBDReady;
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reg RxBDOK;
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reg TxBDReady;
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reg RxBDRead;
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reg [31:0] TxDataLatched;
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reg [1:0] TxByteCnt;
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reg LastWord;
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reg ReadTxDataFromFifo_tck;
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reg BlockingTxStatusWrite;
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reg BlockingTxBDRead;
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reg Flop;
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reg [7:1] TxBDAddress;
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reg [7:1] RxBDAddress;
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reg TxRetrySync1;
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reg TxAbortSync1;
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reg TxDoneSync1;
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reg TxAbort_q;
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reg TxRetry_q;
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reg TxUsedData_q;
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reg [31:0] RxDataLatched2;
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reg [31:8] RxDataLatched1; // Big Endian Byte Ordering
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reg [1:0] RxValidBytes;
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reg [1:0] RxByteCnt;
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reg LastByteIn;
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reg ShiftWillEnd;
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reg WriteRxDataToFifo;
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reg [15:0] LatchedRxLength;
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reg RxAbortLatched;
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reg ShiftEnded;
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reg RxOverrun;
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reg [3:0] BDWrite; // BD Write Enable for access from WISHBONE side
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reg BDRead; // BD Read access from WISHBONE side
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wire [31:0] RxBDDataIn; // Rx BD data in
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wire [31:0] TxBDDataIn; // Tx BD data in
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reg TxEndFrm_wb;
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wire TxRetryPulse;
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wire TxDonePulse;
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wire TxAbortPulse;
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wire StartRxBDRead;
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wire StartTxBDRead;
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wire TxIRQEn;
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wire WrapTxStatusBit;
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wire RxIRQEn;
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wire WrapRxStatusBit;
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wire [1:0] TxValidBytes;
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wire [7:1] TempTxBDAddress;
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wire [7:1] TempRxBDAddress;
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wire RxStatusWrite;
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wire RxBufferFull;
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wire RxBufferAlmostEmpty;
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wire RxBufferEmpty;
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reg WB_ACK_O;
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wire [8:0] RxStatusIn;
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reg [8:0] RxStatusInLatched;
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reg WbEn, WbEn_q;
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reg RxEn, RxEn_q;
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reg TxEn, TxEn_q;
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reg r_TxEn_q;
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reg r_RxEn_q;
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wire ram_ce;
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wire [3:0] ram_we;
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wire ram_oe;
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reg [7:0] ram_addr;
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reg [31:0] ram_di;
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wire [31:0] ram_do;
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wire StartTxPointerRead;
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reg TxPointerRead;
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reg TxEn_needed;
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reg RxEn_needed;
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wire StartRxPointerRead;
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reg RxPointerRead;
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// RX shift ending signals
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reg ShiftEnded_rck;
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reg ShiftEndedSync1;
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reg ShiftEndedSync2;
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reg ShiftEndedSync3;
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reg ShiftEndedSync_c1;
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reg ShiftEndedSync_c2;
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wire StartShiftWillEnd;
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// Pulse for wishbone side having finished writing back
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reg rx_wb_writeback_finished;
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// Indicator of last set of writes from the Wishbone master coming up
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reg rx_wb_last_writes;
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`ifdef TXBD_POLL
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reg [31:0] TxBDReadySamples; // -- jb
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wire TxBDNotReady; // -- jb
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`endif
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`ifdef ETH_WISHBONE_B3
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`ifndef BURST_4BEAT
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assign m_wb_bte_o = 2'b00; // Linear burst
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`endif
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`endif
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assign m_wb_stb_o = m_wb_cyc_o;
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always @ (posedge WB_CLK_I)
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begin
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WB_ACK_O <= (|BDWrite) & WbEn & WbEn_q | BDRead & WbEn & ~WbEn_q;
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end
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assign WB_DAT_O = ram_do;
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// Generic synchronous single-port RAM interface
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eth_spram_256x32
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#(1) // Write enable width
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bd_ram
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(
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.clk (WB_CLK_I),
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.rst (Reset),
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.ce (ram_ce),
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.we (ram_we[0]),
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.oe (ram_oe),
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.addr (ram_addr),
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.di (ram_di),
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.do (ram_do)
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`ifdef ETH_BIST
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,
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.mbist_si_i (mbist_si_i),
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.mbist_so_o (mbist_so_o),
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.mbist_ctrl_i (mbist_ctrl_i)
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`endif
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);
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assign ram_ce = 1'b1;
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assign ram_we = (BDWrite & {4{(WbEn & WbEn_q)}}) |
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{4{(TxStatusWrite | RxStatusWrite)}};
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assign ram_oe = BDRead & WbEn & WbEn_q | TxEn & TxEn_q &
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(TxBDRead | TxPointerRead) | RxEn & RxEn_q &
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(RxBDRead | RxPointerRead);
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always @ (posedge WB_CLK_I or posedge Reset)
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begin
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if(Reset)
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TxEn_needed <= 1'b0;
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else
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if(~TxBDReady & r_TxEn & WbEn & ~WbEn_q)
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TxEn_needed <= 1'b1;
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else
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if(TxPointerRead & TxEn & TxEn_q)
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TxEn_needed <= 1'b0;
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end
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// Enabling access to the RAM for three devices.
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always @ (posedge WB_CLK_I or posedge Reset)
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begin
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if(Reset)
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begin
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WbEn <= 1'b1;
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RxEn <= 1'b0;
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TxEn <= 1'b0;
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ram_addr <= 8'h0;
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ram_di <= 32'h0;
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BDRead <= 1'b0;
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BDWrite <= 1'b0;
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end
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else
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begin
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// Switching between three stages depends on enable signals
|
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case ({WbEn_q, RxEn_q, TxEn_q, RxEn_needed, TxEn_needed}) // synopsys parallel_case
|
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5'b100_10, 5'b100_11 :
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begin
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WbEn <= 1'b0;
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RxEn <= 1'b1; // wb access stage and r_RxEn is enabled
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TxEn <= 1'b0;
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ram_addr <= {RxBDAddress, RxPointerRead};
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ram_di <= RxBDDataIn;
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end
|
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5'b100_01 :
|
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begin
|
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WbEn <= 1'b0;
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RxEn <= 1'b0;
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TxEn <= 1'b1; // wb access stage, r_RxEn is disabled but
|
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// r_TxEn is enabled
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ram_addr <= {TxBDAddress, TxPointerRead};
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ram_di <= TxBDDataIn;
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end
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5'b010_00, 5'b010_10 :
|
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begin
|
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WbEn <= 1'b1; // RxEn access stage and r_TxEn is disabled
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RxEn <= 1'b0;
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TxEn <= 1'b0;
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ram_addr <= WB_ADR_I[9:2];
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ram_di <= WB_DAT_I;
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BDWrite <= BDCs[3:0] & {4{WB_WE_I}};
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BDRead <= (|BDCs) & ~WB_WE_I;
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end
|
|
5'b010_01, 5'b010_11 :
|
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begin
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WbEn <= 1'b0;
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RxEn <= 1'b0;
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TxEn <= 1'b1; // RxEn access stage and r_TxEn is enabled
|
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ram_addr <= {TxBDAddress, TxPointerRead};
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ram_di <= TxBDDataIn;
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end
|
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5'b001_00, 5'b001_01, 5'b001_10, 5'b001_11 :
|
|
begin
|
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WbEn <= 1'b1; // TxEn access stage (we always go to wb
|
|
// access stage)
|
|
RxEn <= 1'b0;
|
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TxEn <= 1'b0;
|
|
ram_addr <= WB_ADR_I[9:2];
|
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ram_di <= WB_DAT_I;
|
|
BDWrite <= BDCs[3:0] & {4{WB_WE_I}};
|
|
BDRead <= (|BDCs) & ~WB_WE_I;
|
|
end
|
|
5'b100_00 :
|
|
begin
|
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WbEn <= 1'b0; // WbEn access stage and there is no need
|
|
// for other stages. WbEn needs to be
|
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// switched off for a bit
|
|
end
|
|
5'b000_00 :
|
|
begin
|
|
WbEn <= 1'b1; // Idle state. We go to WbEn access stage.
|
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RxEn <= 1'b0;
|
|
TxEn <= 1'b0;
|
|
ram_addr <= WB_ADR_I[9:2];
|
|
ram_di <= WB_DAT_I;
|
|
BDWrite <= BDCs[3:0] & {4{WB_WE_I}};
|
|
BDRead <= (|BDCs) & ~WB_WE_I;
|
|
end
|
|
endcase
|
|
end
|
|
end
|
|
|
|
|
|
// Delayed stage signals
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
begin
|
|
WbEn_q <= 1'b0;
|
|
RxEn_q <= 1'b0;
|
|
TxEn_q <= 1'b0;
|
|
r_TxEn_q <= 1'b0;
|
|
r_RxEn_q <= 1'b0;
|
|
end
|
|
else
|
|
begin
|
|
WbEn_q <= WbEn;
|
|
RxEn_q <= RxEn;
|
|
TxEn_q <= TxEn;
|
|
r_TxEn_q <= r_TxEn;
|
|
r_RxEn_q <= r_RxEn;
|
|
end
|
|
end
|
|
|
|
// Changes for tx occur every second clock. Flop is used for this manner.
|
|
always @ (posedge MTxClk or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
Flop <= 1'b0;
|
|
else
|
|
if(TxDone | TxAbort | TxRetry_q)
|
|
Flop <= 1'b0;
|
|
else
|
|
if(TxUsedData)
|
|
Flop <= ~Flop;
|
|
end
|
|
|
|
wire ResetTxBDReady;
|
|
assign ResetTxBDReady = TxDonePulse | TxAbortPulse | TxRetryPulse;
|
|
|
|
// Latching READY status of the Tx buffer descriptor
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
TxBDReady <= 1'b0;
|
|
else
|
|
if(TxEn & TxEn_q & TxBDRead)
|
|
// TxBDReady is sampled only once at the beginning.
|
|
TxBDReady <= ram_do[15] & (ram_do[31:16] > 4);
|
|
else
|
|
// Only packets larger then 4 bytes are transmitted.
|
|
if(ResetTxBDReady)
|
|
TxBDReady <= 1'b0;
|
|
end
|
|
|
|
`ifdef TXBD_POLL
|
|
// Register TxBDReady 4 times, when all are low we know this one is not
|
|
// good to transmit
|
|
always @(posedge WB_CLK_I or posedge Reset) // -- jb
|
|
begin
|
|
if (Reset) TxBDReadySamples <= 32'hffffffff;
|
|
else begin
|
|
if (r_TxEn)
|
|
begin
|
|
if (TxBDNotReady)
|
|
TxBDReadySamples <= 32'hffffffff;
|
|
else
|
|
TxBDReadySamples[31:0] <= {TxBDReadySamples[30:0],TxBDReady};
|
|
end
|
|
else
|
|
TxBDReadySamples <= 32'hffffffff;
|
|
end // else: !if(Reset)
|
|
end // always @ (posedge WB_CLK_I or posedge Reset)
|
|
// When all low, this goes high -- jb
|
|
assign TxBDNotReady = ~(|TxBDReadySamples);
|
|
|
|
|
|
`endif
|
|
|
|
// Reading the Tx buffer descriptor
|
|
assign StartTxBDRead = (TxRetryPacket_NotCleared | TxStatusWrite) &
|
|
~BlockingTxBDRead & ~TxBDReady;
|
|
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
TxBDRead <= 1'b1;
|
|
else
|
|
if(StartTxBDRead)
|
|
TxBDRead <= 1'b1;
|
|
else
|
|
if(TxBDReady)
|
|
TxBDRead <= 1'b0;
|
|
end
|
|
|
|
|
|
// Reading Tx BD pointer
|
|
assign StartTxPointerRead = TxBDRead & TxBDReady;
|
|
|
|
// Reading Tx BD Pointer
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
TxPointerRead <= 1'b0;
|
|
else
|
|
if(StartTxPointerRead)
|
|
TxPointerRead <= 1'b1;
|
|
else
|
|
if(TxEn_q)
|
|
TxPointerRead <= 1'b0;
|
|
end
|
|
|
|
|
|
// Writing status back to the Tx buffer descriptor
|
|
assign TxStatusWrite = (TxDonePacket_NotCleared | TxAbortPacket_NotCleared)&
|
|
TxEn & TxEn_q & ~BlockingTxStatusWrite;
|
|
|
|
|
|
|
|
// Status writing must occur only once. Meanwhile it is blocked.
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
BlockingTxStatusWrite <= 1'b0;
|
|
else
|
|
if(~TxDone_wb & ~TxAbort_wb)
|
|
BlockingTxStatusWrite <= 1'b0;
|
|
else
|
|
if(TxStatusWrite)
|
|
BlockingTxStatusWrite <= 1'b1;
|
|
end
|
|
|
|
|
|
reg BlockingTxStatusWrite_sync1;
|
|
reg BlockingTxStatusWrite_sync2;
|
|
reg BlockingTxStatusWrite_sync3;
|
|
|
|
// Synchronizing BlockingTxStatusWrite to MTxClk
|
|
always @ (posedge MTxClk or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
BlockingTxStatusWrite_sync1 <= 1'b0;
|
|
else
|
|
BlockingTxStatusWrite_sync1 <= BlockingTxStatusWrite;
|
|
end
|
|
|
|
// Synchronizing BlockingTxStatusWrite to MTxClk
|
|
always @ (posedge MTxClk or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
BlockingTxStatusWrite_sync2 <= 1'b0;
|
|
else
|
|
BlockingTxStatusWrite_sync2 <= BlockingTxStatusWrite_sync1;
|
|
end
|
|
|
|
// Synchronizing BlockingTxStatusWrite to MTxClk
|
|
always @ (posedge MTxClk or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
BlockingTxStatusWrite_sync3 <= 1'b0;
|
|
else
|
|
BlockingTxStatusWrite_sync3 <= BlockingTxStatusWrite_sync2;
|
|
end
|
|
|
|
assign RstDeferLatched = BlockingTxStatusWrite_sync2 &
|
|
~BlockingTxStatusWrite_sync3;
|
|
|
|
// TxBDRead state is activated only once.
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
BlockingTxBDRead <= 1'b0;
|
|
else
|
|
if(StartTxBDRead)
|
|
BlockingTxBDRead <= 1'b1;
|
|
else
|
|
if(~StartTxBDRead & ~TxBDReady)
|
|
BlockingTxBDRead <= 1'b0;
|
|
end
|
|
|
|
|
|
// Latching status from the tx buffer descriptor
|
|
// Data is avaliable one cycle after the access is started (at that time
|
|
// signal TxEn is not active)
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
TxStatus <= 4'h0;
|
|
else
|
|
if(TxEn & TxEn_q & TxBDRead)
|
|
TxStatus <= ram_do[14:11];
|
|
end
|
|
|
|
reg ReadTxDataFromMemory;
|
|
wire WriteRxDataToMemory;
|
|
reg WriteRxDataToMemory_r;
|
|
|
|
// Register WriteRxDataToMemory in Wishbone clock domain
|
|
// so it doesn't get out of sync with burst capability indication signals
|
|
always @(posedge WB_CLK_I or posedge Reset)
|
|
if (Reset)
|
|
WriteRxDataToMemory_r <= 0;
|
|
else
|
|
WriteRxDataToMemory_r <= WriteRxDataToMemory;
|
|
|
|
reg MasterWbTX;
|
|
reg MasterWbRX;
|
|
|
|
reg [29:0] m_wb_adr_o;
|
|
reg m_wb_cyc_o;
|
|
reg [3:0] m_wb_sel_o;
|
|
reg m_wb_we_o;
|
|
|
|
wire TxLengthEq0;
|
|
wire TxLengthLt4;
|
|
|
|
reg BlockingIncrementTxPointer;
|
|
reg [31:2] TxPointerMSB;
|
|
reg [1:0] TxPointerLSB;
|
|
reg [1:0] TxPointerLSB_rst;
|
|
reg [31:2] RxPointerMSB;
|
|
reg [1:0] RxPointerLSB_rst;
|
|
|
|
wire RxBurstAcc;
|
|
wire RxWordAcc;
|
|
wire RxHalfAcc;
|
|
wire RxByteAcc;
|
|
|
|
//Latching length from the buffer descriptor;
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
TxLength <= 16'h0;
|
|
else
|
|
if(TxEn & TxEn_q & TxBDRead)
|
|
TxLength <= ram_do[31:16];
|
|
else
|
|
if(MasterWbTX & m_wb_ack_i)
|
|
begin
|
|
if(TxLengthLt4)
|
|
TxLength <= 16'h0;
|
|
else
|
|
if(TxPointerLSB_rst==2'h0)
|
|
TxLength <= TxLength - 3'h4; // Length is subtracted at
|
|
// the data request
|
|
else
|
|
if(TxPointerLSB_rst==2'h1)
|
|
TxLength <= TxLength - 3'h3; // Length is subtracted
|
|
// at the data request
|
|
else
|
|
if(TxPointerLSB_rst==2'h2)
|
|
TxLength <= TxLength - 3'h2; // Length is subtracted
|
|
// at the data request
|
|
else
|
|
if(TxPointerLSB_rst==2'h3)
|
|
TxLength <= TxLength - 3'h1; // Length is subtracted
|
|
// at the data request
|
|
end
|
|
end
|
|
|
|
|
|
|
|
//Latching length from the buffer descriptor;
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
LatchedTxLength <= 16'h0;
|
|
else
|
|
if(TxEn & TxEn_q & TxBDRead)
|
|
LatchedTxLength <= ram_do[31:16];
|
|
end
|
|
|
|
assign TxLengthEq0 = TxLength == 0;
|
|
assign TxLengthLt4 = TxLength < 4;
|
|
|
|
reg cyc_cleared;
|
|
reg IncrTxPointer;
|
|
|
|
|
|
// Latching Tx buffer pointer from buffer descriptor. Only 30 MSB bits are
|
|
// latched because TxPointerMSB is only used for word-aligned accesses.
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
TxPointerMSB <= 30'h0;
|
|
else
|
|
if(TxEn & TxEn_q & TxPointerRead)
|
|
TxPointerMSB <= ram_do[31:2];
|
|
else
|
|
if(IncrTxPointer & ~BlockingIncrementTxPointer)
|
|
// TxPointer is word-aligned
|
|
TxPointerMSB <= TxPointerMSB + 1'b1;
|
|
end
|
|
|
|
|
|
// Latching 2 MSB bits of the buffer descriptor. Since word accesses are
|
|
// performed, valid data does not necesserly start at byte 0 (could be byte
|
|
// 0, 1, 2 or 3). This signals are used for proper selection of the start
|
|
// byte (TxData and TxByteCnt) are set by this two bits.
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
TxPointerLSB[1:0] <= 0;
|
|
else
|
|
if(TxEn & TxEn_q & TxPointerRead)
|
|
TxPointerLSB[1:0] <= ram_do[1:0];
|
|
end
|
|
|
|
|
|
// Latching 2 MSB bits of the buffer descriptor.
|
|
// After the read access, TxLength needs to be decremented for the number of
|
|
// the valid bytes (1 to 4 bytes are valid in the first word). After the
|
|
// first read all bytes are valid so this two bits are reset to zero.
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
TxPointerLSB_rst[1:0] <= 0;
|
|
else
|
|
if(TxEn & TxEn_q & TxPointerRead)
|
|
TxPointerLSB_rst[1:0] <= ram_do[1:0];
|
|
else
|
|
// After first access pointer is word alligned
|
|
if(MasterWbTX & m_wb_ack_i)
|
|
TxPointerLSB_rst[1:0] <= 0;
|
|
end
|
|
|
|
|
|
reg [3:0] RxByteSel;
|
|
wire MasterAccessFinished;
|
|
|
|
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
BlockingIncrementTxPointer <= 0;
|
|
else
|
|
if(MasterAccessFinished)
|
|
BlockingIncrementTxPointer <= 0;
|
|
else
|
|
if(IncrTxPointer)
|
|
BlockingIncrementTxPointer <= 1'b1;
|
|
end
|
|
|
|
|
|
wire TxBufferAlmostFull;
|
|
wire TxBufferFull;
|
|
wire TxBufferEmpty;
|
|
wire TxBufferAlmostEmpty;
|
|
wire SetReadTxDataFromMemory;
|
|
|
|
reg BlockReadTxDataFromMemory;
|
|
|
|
assign SetReadTxDataFromMemory = TxEn & TxEn_q & TxPointerRead;
|
|
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
ReadTxDataFromMemory <= 1'b0;
|
|
else
|
|
if(TxLengthEq0 | TxAbortPulse | TxRetryPulse)
|
|
ReadTxDataFromMemory <= 1'b0;
|
|
else
|
|
if(SetReadTxDataFromMemory)
|
|
ReadTxDataFromMemory <= 1'b1;
|
|
end
|
|
|
|
reg tx_burst_en;
|
|
reg rx_burst_en;
|
|
reg [`ETH_BURST_CNT_WIDTH-1:0] tx_burst_cnt;
|
|
|
|
wire ReadTxDataFromMemory_2;
|
|
wire tx_burst;
|
|
|
|
|
|
wire [31:0] TxData_wb;
|
|
wire ReadTxDataFromFifo_wb;
|
|
|
|
assign ReadTxDataFromMemory_2 = ReadTxDataFromMemory &
|
|
~BlockReadTxDataFromMemory | (|tx_burst_cnt);
|
|
|
|
assign tx_burst = ReadTxDataFromMemory_2 & tx_burst_en;
|
|
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
BlockReadTxDataFromMemory <= 1'b0;
|
|
else
|
|
if((TxBufferAlmostFull | TxLength <= 4)& MasterWbTX &
|
|
(~cyc_cleared) & (!(TxAbortPacket_NotCleared |
|
|
TxRetryPacket_NotCleared)))
|
|
BlockReadTxDataFromMemory <= 1'b1;
|
|
else
|
|
if(ReadTxDataFromFifo_wb | TxDonePacket | TxAbortPacket |
|
|
TxRetryPacket)
|
|
BlockReadTxDataFromMemory <= 1'b0;
|
|
end
|
|
|
|
`define TX_BURST_EN_CONDITION (txfifo_cnt<(`ETH_TX_FIFO_DEPTH-`ETH_BURST_LENGTH) & (TxLength>(`ETH_BURST_LENGTH*4+4)))
|
|
|
|
assign MasterAccessFinished = m_wb_ack_i | m_wb_err_i;
|
|
wire [`ETH_TX_FIFO_CNT_WIDTH-1:0] txfifo_cnt;
|
|
wire [`ETH_RX_FIFO_CNT_WIDTH-1:0] rxfifo_cnt;
|
|
|
|
reg [`ETH_BURST_CNT_WIDTH-1:0] rx_burst_cnt;
|
|
|
|
wire rx_burst;
|
|
wire enough_data_in_rxfifo_for_burst;
|
|
wire enough_data_in_rxfifo_for_burst_plus1;
|
|
|
|
// Enabling master wishbone access to the memory for two devices TX and RX.
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
begin
|
|
MasterWbTX <= 1'b0;
|
|
MasterWbRX <= 1'b0;
|
|
m_wb_adr_o <= 30'h0;
|
|
m_wb_cyc_o <= 1'b0;
|
|
m_wb_we_o <= 1'b0;
|
|
m_wb_sel_o <= 4'h0;
|
|
cyc_cleared<= 1'b0;
|
|
tx_burst_cnt<= 0;
|
|
rx_burst_cnt<= 0;
|
|
IncrTxPointer<= 1'b0;
|
|
tx_burst_en<= 1'b1;
|
|
rx_burst_en<= 1'b0;
|
|
`ifdef ETH_WISHBONE_B3
|
|
m_wb_cti_o <= 3'b0;
|
|
`ifdef BURST_4BEAT
|
|
m_wb_bte_o <= 2'b00;
|
|
`endif
|
|
`endif
|
|
end
|
|
else
|
|
begin
|
|
// Switching between two stages depends on enable signals
|
|
casex ({MasterWbTX,
|
|
MasterWbRX,
|
|
ReadTxDataFromMemory_2,
|
|
WriteRxDataToMemory_r,
|
|
MasterAccessFinished,
|
|
cyc_cleared,
|
|
tx_burst,
|
|
rx_burst}) // synopsys parallel_case
|
|
|
|
8'b00_10_00_10, // Idle and MRB needed
|
|
8'b10_1x_10_1x, // MRB continues
|
|
8'b10_10_01_10, // Clear (previously MR) and MRB needed
|
|
8'b01_1x_01_1x: // Clear (previously MW) and MRB needed
|
|
begin
|
|
MasterWbTX <= 1'b1; // tx burst
|
|
MasterWbRX <= 1'b0;
|
|
m_wb_cyc_o <= 1'b1;
|
|
m_wb_we_o <= 1'b0;
|
|
m_wb_sel_o <= 4'hf;
|
|
cyc_cleared<= 1'b0;
|
|
IncrTxPointer<= 1'b1;
|
|
tx_burst_cnt <= tx_burst_cnt+3'h1;
|
|
if(tx_burst_cnt==0)
|
|
m_wb_adr_o <= TxPointerMSB;
|
|
else
|
|
m_wb_adr_o <= m_wb_adr_o+1'b1;
|
|
|
|
if(tx_burst_cnt==(`ETH_BURST_LENGTH-1))
|
|
begin
|
|
tx_burst_en<= 1'b0;
|
|
`ifdef ETH_WISHBONE_B3
|
|
m_wb_cti_o <= 3'b111;
|
|
`endif
|
|
end
|
|
else
|
|
begin
|
|
`ifdef ETH_WISHBONE_B3
|
|
m_wb_cti_o <= 3'b010;
|
|
`ifdef BURST_4BEAT
|
|
m_wb_bte_o <= 2'b01;
|
|
`endif
|
|
`endif
|
|
end
|
|
end // case: 8'b00_10_00_10,...
|
|
`ifdef ETH_RX_BURST_EN
|
|
8'b00_x1_00_x1, // Idle and MWB needed
|
|
8'b01_x1_10_x1, // MWB continues
|
|
8'b01_01_01_01, // Clear (previously MW) and MWB needed
|
|
8'b10_x1_01_x1 : // Clear (previously MR) and MWB needed
|
|
begin
|
|
MasterWbTX <= 1'b0; // rx burst
|
|
MasterWbRX <= 1'b1;
|
|
m_wb_cyc_o <= 1'b1;
|
|
m_wb_we_o <= 1'b1;
|
|
m_wb_sel_o <= RxByteSel;
|
|
IncrTxPointer<= 1'b0;
|
|
cyc_cleared<= 1'b0;
|
|
rx_burst_cnt <= rx_burst_cnt+3'h1;
|
|
|
|
if(rx_burst_cnt==0)
|
|
m_wb_adr_o <= RxPointerMSB;
|
|
else
|
|
m_wb_adr_o <= m_wb_adr_o+1'b1;
|
|
|
|
if(rx_burst_cnt==(`ETH_BURST_LENGTH-1))
|
|
begin
|
|
rx_burst_en<= 1'b0;
|
|
`ifdef ETH_WISHBONE_B3
|
|
m_wb_cti_o <= 3'b111;
|
|
`endif
|
|
end
|
|
else
|
|
begin
|
|
`ifdef ETH_WISHBONE_B3
|
|
`ifdef BURST_4BEAT
|
|
m_wb_cti_o <= 3'b010;
|
|
m_wb_bte_o <= 2'b01;
|
|
`endif
|
|
`endif
|
|
end
|
|
end // case: 8'b00_x1_00_x1,...
|
|
`endif // `ifdef ETH_RX_BURST_EN
|
|
8'b00_x1_00_x0 ,//idle and MW is needed (data write to rx buffer)
|
|
8'b01_x1_00_x0 :// Sometimes gets caught changing states - JB
|
|
begin
|
|
MasterWbTX <= 1'b0;
|
|
MasterWbRX <= !RxBufferEmpty;
|
|
m_wb_adr_o <= RxPointerMSB;
|
|
m_wb_cyc_o <= !RxBufferEmpty;
|
|
m_wb_we_o <= !RxBufferEmpty;
|
|
m_wb_sel_o <= RxByteSel;
|
|
IncrTxPointer<= 1'b0;
|
|
`ifdef ETH_WISHBONE_B3
|
|
`ifdef ETH_RX_BURST_EN
|
|
`ifdef BURST_4BEAT
|
|
if ((RxPointerMSB[3:2]==2'b00) & !RxBufferEmpty &
|
|
enough_data_in_rxfifo_for_burst & !m_wb_cyc_o)
|
|
// Added "& !_m_wb_cyc_o" here to stop burst signals
|
|
// going high during a transfer
|
|
begin
|
|
rx_burst_en<= 1'b1;
|
|
m_wb_cti_o <= 3'b010;
|
|
m_wb_bte_o <= 2'b01;
|
|
rx_burst_cnt<= 1;
|
|
end
|
|
`endif
|
|
`endif
|
|
`endif // `ifdef ETH_WISHBONE_B3
|
|
|
|
end
|
|
8'b00_10_00_00 : // idle and MR is needed (data read from tx
|
|
// buffer)
|
|
begin
|
|
MasterWbTX <= 1'b1;
|
|
MasterWbRX <= 1'b0;
|
|
m_wb_adr_o <= TxPointerMSB;
|
|
m_wb_cyc_o <= 1'b1;
|
|
m_wb_we_o <= 1'b0;
|
|
m_wb_sel_o <= 4'hf;
|
|
IncrTxPointer<= 1'b1;
|
|
`ifdef BURST_4BEAT
|
|
|
|
// Attempt ethernet bugfix, start bursts later
|
|
if ((TxPointerMSB[3:2]==2'b00) && `TX_BURST_EN_CONDITION)
|
|
begin
|
|
`ifdef TX_BURST_EN_VERBOSE
|
|
$display("(%t)(%m): %b enabling tx_burst_en",$time,
|
|
{MasterWbTX,MasterWbRX,ReadTxDataFromMemory_2,
|
|
WriteRxDataToMemory,MasterAccessFinished,
|
|
cyc_cleared,tx_burst,rx_burst});
|
|
`endif
|
|
tx_burst_en<= 1'b1;
|
|
tx_burst_cnt <= 3'h1;
|
|
|
|
`ifdef ETH_WISHBONE_B3
|
|
m_wb_cti_o <= 3'b010;
|
|
m_wb_bte_o <= 2'b01;
|
|
`endif
|
|
end
|
|
`endif
|
|
end
|
|
8'b10_10_01_00,// MR and MR is needed (data read from tx buffer)
|
|
8'b01_1x_01_0x :// MW and MR is needed (data read from tx
|
|
// buffer)
|
|
begin
|
|
MasterWbTX <= 1'b1; // Only switch to TX here
|
|
// when not end of RX
|
|
MasterWbRX <= 1'b0;
|
|
m_wb_adr_o <= TxPointerMSB;
|
|
m_wb_cyc_o <= 1'b1;
|
|
m_wb_we_o <= 1'b0;
|
|
m_wb_sel_o <= 4'hf;
|
|
cyc_cleared<= 1'b0;
|
|
IncrTxPointer<= 1'b1;
|
|
`ifdef BURST_4BEAT
|
|
if ((TxPointerMSB[3:2]==2'b00) & `TX_BURST_EN_CONDITION)
|
|
begin
|
|
`ifdef TX_BURST_EN_VERBOSE
|
|
$display("(%t)(%m): %b enabling tx_burst_en",$time,
|
|
{MasterWbTX,MasterWbRX,
|
|
ReadTxDataFromMemory_2,
|
|
WriteRxDataToMemory,
|
|
MasterAccessFinished,
|
|
cyc_cleared,
|
|
tx_burst,
|
|
rx_burst});
|
|
`endif
|
|
tx_burst_en<= 1'b1;
|
|
tx_burst_cnt <= 3'h1;
|
|
`ifdef ETH_WISHBONE_B3
|
|
m_wb_cti_o <= 3'b010;
|
|
m_wb_bte_o <= 2'b01;
|
|
`endif
|
|
end
|
|
`endif
|
|
|
|
end
|
|
8'b01_01_01_00,// MW and MW needed (data write to rx buffer)
|
|
8'b10_x1_01_x0 ://MR and MW is needed (data write to rx buffer)
|
|
begin
|
|
MasterWbTX <= 1'b0;
|
|
MasterWbRX <= !RxBufferEmpty;
|
|
rx_burst_cnt<= 0;
|
|
m_wb_adr_o <= RxPointerMSB;
|
|
m_wb_cyc_o <= !RxBufferEmpty;
|
|
m_wb_we_o <= !RxBufferEmpty;
|
|
m_wb_sel_o <= RxByteSel;
|
|
`ifdef ETH_WISHBONE_B3
|
|
`ifdef ETH_RX_BURST_EN
|
|
`ifdef BURST_4BEAT
|
|
if ((RxPointerMSB[3:2]==2'b00) &
|
|
enough_data_in_rxfifo_for_burst & !RxBufferEmpty)
|
|
//enough_data_in_rxfifo_for_burst_plus1)
|
|
|
|
|
|
begin
|
|
rx_burst_en<= 1'b1;
|
|
m_wb_cti_o <= 3'b010;
|
|
m_wb_bte_o <= 2'b01;
|
|
rx_burst_cnt<= 1;
|
|
end
|
|
`endif
|
|
`endif // `ifdef ETH_RX_BURST_EN
|
|
`endif // `ifdef ETH_WISHBONE_B3
|
|
cyc_cleared<= 1'b0;
|
|
IncrTxPointer<= 1'b0;
|
|
end
|
|
8'b01_01_10_00,// MW and MW needed (cycle is cleared between
|
|
// previous and next access)
|
|
8'b01_1x_10_x0,// MW and MW or MR or MRB needed (cycle is
|
|
// cleared between previous and next access)
|
|
8'b10_10_10_00,// MR and MR needed (cycle is cleared between
|
|
// previous and next access)
|
|
8'b10_x1_10_0x :// MR and MR or MW or MWB (cycle is cleared
|
|
// between previous and next access)
|
|
begin
|
|
m_wb_cyc_o <= 1'b0;// whatever and master read or write is
|
|
// needed. We need to clear m_wb_cyc_o
|
|
// before next access is started
|
|
cyc_cleared<= 1'b1;
|
|
IncrTxPointer<= 1'b0;
|
|
tx_burst_cnt<= 0;
|
|
`ifdef BURST_4BEAT
|
|
// Caused a bug!
|
|
// if (TxPointerMSB[3:2]==2'b00)
|
|
//tx_burst_en<= `TX_BURST_EN_CONDITION;
|
|
// Set this to 0 here
|
|
tx_burst_en<= 0;
|
|
|
|
`endif
|
|
rx_burst_cnt<= 0;
|
|
`ifdef ETH_WISHBONE_B3
|
|
m_wb_bte_o <= 2'b00;
|
|
m_wb_cti_o <= 3'b0;
|
|
`endif
|
|
end
|
|
8'bxx_00_10_00,// whatever and no master read or write is needed
|
|
// (ack or err comes finishing previous access)
|
|
8'bxx_00_01_00 : // Between cyc_cleared request was cleared
|
|
begin
|
|
MasterWbTX <= 1'b0;
|
|
MasterWbRX <= 1'b0;
|
|
m_wb_cyc_o <= 1'b0;
|
|
cyc_cleared<= 1'b0;
|
|
IncrTxPointer<= 1'b0;
|
|
rx_burst_cnt<= 0;
|
|
m_wb_bte_o <= 2'b00;
|
|
m_wb_cti_o <= 3'b0;
|
|
end
|
|
8'b00_00_00_00: // whatever and no master read or write is
|
|
// needed (ack or err comes finishing previous
|
|
// access)
|
|
begin
|
|
tx_burst_cnt<= 0;
|
|
`ifdef BURST_4BEAT
|
|
|
|
// This caused tx_burst to remain set between
|
|
// transmits, and sometimes we would burst immediately
|
|
// and maybe get the wrong data because the offset of
|
|
// the buffer pointer wasn't 16-byte aligned.
|
|
//if (TxPointerMSB[3:2]==2'b00)
|
|
// tx_burst_en<= `TX_BURST_EN_CONDITION;
|
|
|
|
// Fix for transmit problems... maybe - jb
|
|
if(TxEn & TxEn_q & TxPointerRead & (ram_do[3:0]===4'h0))
|
|
begin
|
|
`ifdef TX_BURST_EN_VERBOSE
|
|
$display("(%t)(%m): %b enabling tx_burst_en",$time,
|
|
{MasterWbTX,MasterWbRX,ReadTxDataFromMemory_2,
|
|
WriteRxDataToMemory,MasterAccessFinished,
|
|
cyc_cleared,tx_burst,rx_burst});
|
|
`endif
|
|
tx_burst_en<= `TX_BURST_EN_CONDITION;
|
|
end
|
|
else
|
|
tx_burst_en<= 0;
|
|
`endif
|
|
end
|
|
default: // Don't touch
|
|
begin
|
|
MasterWbTX <= MasterWbTX;
|
|
MasterWbRX <= MasterWbRX;
|
|
m_wb_cyc_o <= m_wb_cyc_o;
|
|
m_wb_sel_o <= m_wb_sel_o;
|
|
IncrTxPointer<= IncrTxPointer;
|
|
end
|
|
endcase
|
|
end
|
|
end
|
|
|
|
|
|
wire TxFifoClear;
|
|
|
|
assign TxFifoClear = (TxAbortPacket | TxRetryPacket | StartTxPointerRead);
|
|
|
|
eth_fifo
|
|
#(
|
|
`ETH_TX_FIFO_DATA_WIDTH,
|
|
`ETH_TX_FIFO_DEPTH,
|
|
`ETH_TX_FIFO_CNT_WIDTH
|
|
)
|
|
tx_fifo
|
|
(
|
|
.data_in(m_wb_dat_i),
|
|
.data_out(TxData_wb),
|
|
.clk(WB_CLK_I),
|
|
.reset(Reset),
|
|
.write(MasterWbTX & m_wb_ack_i),
|
|
.read(ReadTxDataFromFifo_wb & ~TxBufferEmpty),
|
|
.clear(TxFifoClear),
|
|
.full(TxBufferFull),
|
|
.almost_full(TxBufferAlmostFull),
|
|
.almost_empty(TxBufferAlmostEmpty),
|
|
.empty(TxBufferEmpty),
|
|
.cnt(txfifo_cnt)
|
|
);
|
|
|
|
|
|
reg StartOccured;
|
|
reg TxStartFrm_sync1;
|
|
reg TxStartFrm_sync2;
|
|
reg TxStartFrm_syncb1;
|
|
reg TxStartFrm_syncb2;
|
|
|
|
|
|
|
|
// Start: Generation of the TxStartFrm_wb which is then synchronized to the MTxClk
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
TxStartFrm_wb <= 1'b0;
|
|
else
|
|
if(TxBDReady & ~StartOccured & (TxBufferFull | TxLengthEq0))
|
|
TxStartFrm_wb <= 1'b1;
|
|
else
|
|
if(TxStartFrm_syncb2)
|
|
TxStartFrm_wb <= 1'b0;
|
|
end
|
|
|
|
// StartOccured: TxStartFrm_wb occurs only ones at the beginning. Then it's
|
|
// blocked.
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
StartOccured <= 1'b0;
|
|
else
|
|
if(TxStartFrm_wb)
|
|
StartOccured <= 1'b1;
|
|
else
|
|
if(ResetTxBDReady)
|
|
StartOccured <= 1'b0;
|
|
end
|
|
|
|
// Synchronizing TxStartFrm_wb to MTxClk
|
|
always @ (posedge MTxClk or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
TxStartFrm_sync1 <= 1'b0;
|
|
else
|
|
TxStartFrm_sync1 <= TxStartFrm_wb;
|
|
end
|
|
|
|
always @ (posedge MTxClk or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
TxStartFrm_sync2 <= 1'b0;
|
|
else
|
|
TxStartFrm_sync2 <= TxStartFrm_sync1;
|
|
end
|
|
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
TxStartFrm_syncb1 <= 1'b0;
|
|
else
|
|
TxStartFrm_syncb1 <= TxStartFrm_sync2;
|
|
end
|
|
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
TxStartFrm_syncb2 <= 1'b0;
|
|
else
|
|
TxStartFrm_syncb2 <= TxStartFrm_syncb1;
|
|
end
|
|
|
|
always @ (posedge MTxClk or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
TxStartFrm <= 1'b0;
|
|
else
|
|
if(TxStartFrm_sync2)
|
|
TxStartFrm <= 1'b1;
|
|
else
|
|
if(TxUsedData_q | ~TxStartFrm_sync2 &
|
|
(TxRetry & (~TxRetry_q) | TxAbort & (~TxAbort_q)))
|
|
TxStartFrm <= 1'b0;
|
|
end
|
|
// End: Generation of the TxStartFrm_wb which is then synchronized to the
|
|
// MTxClk
|
|
|
|
|
|
// TxEndFrm_wb: indicator of the end of frame
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
TxEndFrm_wb <= 1'b0;
|
|
else
|
|
if(TxLengthEq0 & TxBufferAlmostEmpty & TxUsedData)
|
|
TxEndFrm_wb <= 1'b1;
|
|
else
|
|
if(TxRetryPulse | TxDonePulse | TxAbortPulse)
|
|
TxEndFrm_wb <= 1'b0;
|
|
end
|
|
|
|
|
|
// Marks which bytes are valid within the word.
|
|
assign TxValidBytes = TxLengthLt4 ? TxLength[1:0] : 2'b0;
|
|
|
|
reg LatchValidBytes;
|
|
reg LatchValidBytes_q;
|
|
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
LatchValidBytes <= 1'b0;
|
|
else
|
|
if(TxLengthLt4 & TxBDReady)
|
|
LatchValidBytes <= 1'b1;
|
|
else
|
|
LatchValidBytes <= 1'b0;
|
|
end
|
|
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
LatchValidBytes_q <= 1'b0;
|
|
else
|
|
LatchValidBytes_q <= LatchValidBytes;
|
|
end
|
|
|
|
|
|
// Latching valid bytes
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
TxValidBytesLatched <= 2'h0;
|
|
else
|
|
if(LatchValidBytes & ~LatchValidBytes_q)
|
|
TxValidBytesLatched <= TxValidBytes;
|
|
else
|
|
if(TxRetryPulse | TxDonePulse | TxAbortPulse)
|
|
TxValidBytesLatched <= 2'h0;
|
|
end
|
|
|
|
|
|
assign TxIRQEn = TxStatus[14];
|
|
assign WrapTxStatusBit = TxStatus[13];
|
|
assign PerPacketPad = TxStatus[12];
|
|
assign PerPacketCrcEn = TxStatus[11];
|
|
|
|
|
|
assign RxIRQEn = RxStatus[14];
|
|
assign WrapRxStatusBit = RxStatus[13];
|
|
|
|
|
|
// Temporary Tx and Rx buffer descriptor address
|
|
`ifdef TXBD_POLL
|
|
assign TempTxBDAddress[7:1] = {7{ (TxStatusWrite|TxBDNotReady) & ~WrapTxStatusBit}} & (TxBDAddress + 1'b1) ; // Tx BD increment or wrap (last BD) -- jb
|
|
`else
|
|
assign TempTxBDAddress[7:1] = {7{ TxStatusWrite & ~WrapTxStatusBit}} & (TxBDAddress + 1'b1) ; // Tx BD increment or wrap (last BD)
|
|
`endif
|
|
assign TempRxBDAddress[7:1] = {7{ WrapRxStatusBit}} & (r_TxBDNum[6:0]) | // Using first Rx BD
|
|
{7{~WrapRxStatusBit}} & (RxBDAddress + 1'b1) ; // Using next Rx BD (incremenrement address)
|
|
|
|
|
|
// Latching Tx buffer descriptor address
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
TxBDAddress <= 7'h0;
|
|
else if (r_TxEn & (~r_TxEn_q))
|
|
TxBDAddress <= 7'h0;
|
|
`ifdef TXBD_POLL
|
|
else if (TxStatusWrite | TxBDNotReady) // -- jb
|
|
`else
|
|
else if (TxStatusWrite)
|
|
`endif
|
|
TxBDAddress <= TempTxBDAddress;
|
|
end
|
|
|
|
|
|
// Latching Rx buffer descriptor address
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
RxBDAddress <= 7'h0;
|
|
else if(r_RxEn & (~r_RxEn_q))
|
|
RxBDAddress <= r_TxBDNum[6:0];
|
|
else if(RxStatusWrite)
|
|
RxBDAddress <= TempRxBDAddress;
|
|
end
|
|
|
|
wire [8:0] TxStatusInLatched = {TxUnderRun, RetryCntLatched[3:0],
|
|
RetryLimit, LateCollLatched, DeferLatched,
|
|
CarrierSenseLost};
|
|
|
|
assign RxBDDataIn = {LatchedRxLength, 1'b0, RxStatus, 4'h0,
|
|
RxStatusInLatched};
|
|
assign TxBDDataIn = {LatchedTxLength, 1'b0, TxStatus, 2'h0,
|
|
TxStatusInLatched};
|
|
|
|
|
|
// Signals used for various purposes
|
|
assign TxRetryPulse = TxRetry_wb & ~TxRetry_wb_q;
|
|
assign TxDonePulse = TxDone_wb & ~TxDone_wb_q;
|
|
assign TxAbortPulse = TxAbort_wb & ~TxAbort_wb_q;
|
|
|
|
|
|
|
|
// Generating delayed signals
|
|
always @ (posedge MTxClk or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
begin
|
|
TxAbort_q <= 1'b0;
|
|
TxRetry_q <= 1'b0;
|
|
TxUsedData_q <= 1'b0;
|
|
end
|
|
else
|
|
begin
|
|
TxAbort_q <= TxAbort;
|
|
TxRetry_q <= TxRetry;
|
|
TxUsedData_q <= TxUsedData;
|
|
end
|
|
end
|
|
|
|
// Generating delayed signals
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
begin
|
|
TxDone_wb_q <= 1'b0;
|
|
TxAbort_wb_q <= 1'b0;
|
|
TxRetry_wb_q <= 1'b0;
|
|
end
|
|
else
|
|
begin
|
|
TxDone_wb_q <= TxDone_wb;
|
|
TxAbort_wb_q <= TxAbort_wb;
|
|
TxRetry_wb_q <= TxRetry_wb;
|
|
end
|
|
end
|
|
|
|
|
|
reg TxAbortPacketBlocked;
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
TxAbortPacket <= 1'b0;
|
|
else
|
|
if(TxAbort_wb & (~tx_burst_en) & MasterWbTX & MasterAccessFinished &
|
|
(~TxAbortPacketBlocked) | TxAbort_wb & (~MasterWbTX) &
|
|
(~TxAbortPacketBlocked))
|
|
TxAbortPacket <= 1'b1;
|
|
else
|
|
TxAbortPacket <= 1'b0;
|
|
end
|
|
|
|
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
TxAbortPacket_NotCleared <= 1'b0;
|
|
else
|
|
if(TxEn & TxEn_q & TxAbortPacket_NotCleared)
|
|
TxAbortPacket_NotCleared <= 1'b0;
|
|
else
|
|
if(TxAbort_wb & (~tx_burst_en) & MasterWbTX &
|
|
MasterAccessFinished & (~TxAbortPacketBlocked) | TxAbort_wb &
|
|
(~MasterWbTX) & (~TxAbortPacketBlocked))
|
|
TxAbortPacket_NotCleared <= 1'b1;
|
|
end
|
|
|
|
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
TxAbortPacketBlocked <= 1'b0;
|
|
else
|
|
if(!TxAbort_wb & TxAbort_wb_q)
|
|
TxAbortPacketBlocked <= 1'b0;
|
|
else
|
|
if(TxAbortPacket)
|
|
TxAbortPacketBlocked <= 1'b1;
|
|
end
|
|
|
|
|
|
reg TxRetryPacketBlocked;
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
TxRetryPacket <= 1'b0;
|
|
else
|
|
if(TxRetry_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished &
|
|
!TxRetryPacketBlocked | TxRetry_wb & !MasterWbTX &
|
|
!TxRetryPacketBlocked)
|
|
TxRetryPacket <= 1'b1;
|
|
else
|
|
TxRetryPacket <= 1'b0;
|
|
end
|
|
|
|
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
TxRetryPacket_NotCleared <= 1'b0;
|
|
else
|
|
if(StartTxBDRead)
|
|
TxRetryPacket_NotCleared <= 1'b0;
|
|
else
|
|
if(TxRetry_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished &
|
|
!TxRetryPacketBlocked | TxRetry_wb & !MasterWbTX &
|
|
!TxRetryPacketBlocked)
|
|
TxRetryPacket_NotCleared <= 1'b1;
|
|
end
|
|
|
|
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
TxRetryPacketBlocked <= 1'b0;
|
|
else
|
|
if(!TxRetry_wb & TxRetry_wb_q)
|
|
TxRetryPacketBlocked <= 1'b0;
|
|
else
|
|
if(TxRetryPacket)
|
|
TxRetryPacketBlocked <= 1'b1;
|
|
end
|
|
|
|
|
|
reg TxDonePacketBlocked;
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
TxDonePacket <= 1'b0;
|
|
else
|
|
if(TxDone_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished &
|
|
!TxDonePacketBlocked | TxDone_wb & !MasterWbTX &
|
|
!TxDonePacketBlocked)
|
|
TxDonePacket <= 1'b1;
|
|
else
|
|
TxDonePacket <= 1'b0;
|
|
end
|
|
|
|
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
TxDonePacket_NotCleared <= 1'b0;
|
|
else
|
|
if(TxEn & TxEn_q & TxDonePacket_NotCleared)
|
|
TxDonePacket_NotCleared <= 1'b0;
|
|
else
|
|
if(TxDone_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished
|
|
& (~TxDonePacketBlocked) | TxDone_wb & !MasterWbTX
|
|
& (~TxDonePacketBlocked))
|
|
TxDonePacket_NotCleared <= 1'b1;
|
|
end
|
|
|
|
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
TxDonePacketBlocked <= 1'b0;
|
|
else
|
|
if(!TxDone_wb & TxDone_wb_q)
|
|
TxDonePacketBlocked <= 1'b0;
|
|
else
|
|
if(TxDonePacket)
|
|
TxDonePacketBlocked <= 1'b1;
|
|
end
|
|
|
|
|
|
// Indication of the last word
|
|
always @ (posedge MTxClk or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
LastWord <= 1'b0;
|
|
else
|
|
if((TxEndFrm | TxAbort | TxRetry) & Flop)
|
|
LastWord <= 1'b0;
|
|
else
|
|
if(TxUsedData & Flop & TxByteCnt == 2'h3)
|
|
LastWord <= TxEndFrm_wb;
|
|
end
|
|
|
|
|
|
// Tx end frame generation
|
|
always @ (posedge MTxClk or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
TxEndFrm <= 1'b0;
|
|
else
|
|
if(Flop & TxEndFrm | TxAbort | TxRetry_q)
|
|
TxEndFrm <= 1'b0;
|
|
else
|
|
if(Flop & LastWord)
|
|
begin
|
|
case (TxValidBytesLatched) // synopsys parallel_case
|
|
1 : TxEndFrm <= TxByteCnt == 2'h0;
|
|
2 : TxEndFrm <= TxByteCnt == 2'h1;
|
|
3 : TxEndFrm <= TxByteCnt == 2'h2;
|
|
0 : TxEndFrm <= TxByteCnt == 2'h3;
|
|
default : TxEndFrm <= 1'b0;
|
|
endcase
|
|
end
|
|
end
|
|
|
|
|
|
// Tx data selection (latching)
|
|
always @ (posedge MTxClk or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
TxData <= 0;
|
|
else
|
|
if(TxStartFrm_sync2 & ~TxStartFrm)
|
|
case(TxPointerLSB) // synopsys parallel_case
|
|
2'h0 : TxData <= TxData_wb[31:24];// Big Endian Byte Ordering
|
|
2'h1 : TxData <= TxData_wb[23:16];// Big Endian Byte Ordering
|
|
2'h2 : TxData <= TxData_wb[15:08];// Big Endian Byte Ordering
|
|
2'h3 : TxData <= TxData_wb[07:00];// Big Endian Byte Ordering
|
|
endcase
|
|
else
|
|
if(TxStartFrm & TxUsedData & TxPointerLSB==2'h3)
|
|
TxData <= TxData_wb[31:24];// Big Endian Byte Ordering
|
|
else
|
|
if(TxUsedData & Flop)
|
|
begin
|
|
case(TxByteCnt) // synopsys parallel_case
|
|
// Big Endian Byte Ordering
|
|
0 : TxData <= TxDataLatched[31:24];
|
|
1 : TxData <= TxDataLatched[23:16];
|
|
2 : TxData <= TxDataLatched[15:8];
|
|
3 : TxData <= TxDataLatched[7:0];
|
|
endcase
|
|
end
|
|
end
|
|
|
|
|
|
// Latching tx data
|
|
always @ (posedge MTxClk or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
TxDataLatched[31:0] <= 32'h0;
|
|
else
|
|
if(TxStartFrm_sync2 & ~TxStartFrm | TxUsedData & Flop &
|
|
TxByteCnt == 2'h3 | TxStartFrm & TxUsedData & Flop &
|
|
TxByteCnt == 2'h0)
|
|
TxDataLatched[31:0] <= TxData_wb[31:0];
|
|
end
|
|
|
|
|
|
// Tx under run
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
TxUnderRun_wb <= 1'b0;
|
|
else
|
|
if(TxAbortPulse)
|
|
TxUnderRun_wb <= 1'b0;
|
|
else
|
|
if(TxBufferEmpty & ReadTxDataFromFifo_wb)
|
|
TxUnderRun_wb <= 1'b1;
|
|
end
|
|
|
|
|
|
reg TxUnderRun_sync1;
|
|
|
|
// Tx under run
|
|
always @ (posedge MTxClk or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
TxUnderRun_sync1 <= 1'b0;
|
|
else
|
|
if(TxUnderRun_wb)
|
|
TxUnderRun_sync1 <= 1'b1;
|
|
else
|
|
if(BlockingTxStatusWrite_sync2)
|
|
TxUnderRun_sync1 <= 1'b0;
|
|
end
|
|
|
|
// Tx under run
|
|
always @ (posedge MTxClk or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
TxUnderRun <= 1'b0;
|
|
else
|
|
if(BlockingTxStatusWrite_sync2)
|
|
TxUnderRun <= 1'b0;
|
|
else
|
|
if(TxUnderRun_sync1)
|
|
TxUnderRun <= 1'b1;
|
|
end
|
|
|
|
|
|
// Tx Byte counter
|
|
always @ (posedge MTxClk or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
TxByteCnt <= 2'h0;
|
|
else
|
|
if(TxAbort_q | TxRetry_q)
|
|
TxByteCnt <= 2'h0;
|
|
else
|
|
if(TxStartFrm & ~TxUsedData)
|
|
case(TxPointerLSB) // synopsys parallel_case
|
|
2'h0 : TxByteCnt <= 2'h1;
|
|
2'h1 : TxByteCnt <= 2'h2;
|
|
2'h2 : TxByteCnt <= 2'h3;
|
|
2'h3 : TxByteCnt <= 2'h0;
|
|
endcase
|
|
else
|
|
if(TxUsedData & Flop)
|
|
TxByteCnt <= TxByteCnt + 1'b1;
|
|
end
|
|
|
|
|
|
// Start: Generation of the ReadTxDataFromFifo_tck signal and synchronization to the WB_CLK_I
|
|
reg ReadTxDataFromFifo_sync1;
|
|
reg ReadTxDataFromFifo_sync2;
|
|
reg ReadTxDataFromFifo_sync3;
|
|
reg ReadTxDataFromFifo_syncb1;
|
|
reg ReadTxDataFromFifo_syncb2;
|
|
reg ReadTxDataFromFifo_syncb3;
|
|
|
|
|
|
always @ (posedge MTxClk or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
ReadTxDataFromFifo_tck <= 1'b0;
|
|
else
|
|
if(TxStartFrm_sync2 & ~TxStartFrm | TxUsedData & Flop &
|
|
TxByteCnt == 2'h3 & ~LastWord | TxStartFrm & TxUsedData & Flop &
|
|
TxByteCnt == 2'h0)
|
|
ReadTxDataFromFifo_tck <= 1'b1;
|
|
else
|
|
if(ReadTxDataFromFifo_syncb2 & ~ReadTxDataFromFifo_syncb3)
|
|
ReadTxDataFromFifo_tck <= 1'b0;
|
|
end
|
|
|
|
// Synchronizing TxStartFrm_wb to MTxClk
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
ReadTxDataFromFifo_sync1 <= 1'b0;
|
|
else
|
|
ReadTxDataFromFifo_sync1 <= ReadTxDataFromFifo_tck;
|
|
end
|
|
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
ReadTxDataFromFifo_sync2 <= 1'b0;
|
|
else
|
|
ReadTxDataFromFifo_sync2 <= ReadTxDataFromFifo_sync1;
|
|
end
|
|
|
|
always @ (posedge MTxClk or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
ReadTxDataFromFifo_syncb1 <= 1'b0;
|
|
else
|
|
ReadTxDataFromFifo_syncb1 <= ReadTxDataFromFifo_sync2;
|
|
end
|
|
|
|
always @ (posedge MTxClk or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
ReadTxDataFromFifo_syncb2 <= 1'b0;
|
|
else
|
|
ReadTxDataFromFifo_syncb2 <= ReadTxDataFromFifo_syncb1;
|
|
end
|
|
|
|
always @ (posedge MTxClk or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
ReadTxDataFromFifo_syncb3 <= 1'b0;
|
|
else
|
|
ReadTxDataFromFifo_syncb3 <= ReadTxDataFromFifo_syncb2;
|
|
end
|
|
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
ReadTxDataFromFifo_sync3 <= 1'b0;
|
|
else
|
|
ReadTxDataFromFifo_sync3 <= ReadTxDataFromFifo_sync2;
|
|
end
|
|
|
|
assign ReadTxDataFromFifo_wb = ReadTxDataFromFifo_sync2 &
|
|
~ReadTxDataFromFifo_sync3;
|
|
// End: Generation of the ReadTxDataFromFifo_tck signal and synchronization
|
|
// to the WB_CLK_I
|
|
|
|
|
|
// Synchronizing TxRetry signal (synchronized to WISHBONE clock)
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
TxRetrySync1 <= 1'b0;
|
|
else
|
|
TxRetrySync1 <= TxRetry;
|
|
end
|
|
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
TxRetry_wb <= 1'b0;
|
|
else
|
|
TxRetry_wb <= TxRetrySync1;
|
|
end
|
|
|
|
|
|
// Synchronized TxDone_wb signal (synchronized to WISHBONE clock)
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
TxDoneSync1 <= 1'b0;
|
|
else
|
|
TxDoneSync1 <= TxDone;
|
|
end
|
|
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
TxDone_wb <= 1'b0;
|
|
else
|
|
TxDone_wb <= TxDoneSync1;
|
|
end
|
|
|
|
// Synchronizing TxAbort signal (synchronized to WISHBONE clock)
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
TxAbortSync1 <= 1'b0;
|
|
else
|
|
TxAbortSync1 <= TxAbort;
|
|
end
|
|
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
TxAbort_wb <= 1'b0;
|
|
else
|
|
TxAbort_wb <= TxAbortSync1;
|
|
end
|
|
|
|
|
|
reg RxAbortSync1;
|
|
reg RxAbortSync2;
|
|
reg RxAbortSync3;
|
|
reg RxAbortSync4;
|
|
reg RxAbortSyncb1;
|
|
reg RxAbortSyncb2;
|
|
|
|
assign StartRxBDRead = RxStatusWrite | RxAbortSync3 & ~RxAbortSync4 |
|
|
r_RxEn & ~r_RxEn_q;
|
|
|
|
// Reading the Rx buffer descriptor
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
RxBDRead <= 1'b0;
|
|
else
|
|
if(StartRxBDRead)
|
|
RxBDRead <= 1'b1;
|
|
else
|
|
if(RxBDReady)
|
|
RxBDRead <= 1'b0;
|
|
end
|
|
|
|
|
|
// Reading of the next receive buffer descriptor starts after reception
|
|
// status is written to the previous one.
|
|
|
|
// Latching READY status of the Rx buffer descriptor
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
RxBDReady <= 1'b0;
|
|
else
|
|
if(RxPointerRead)
|
|
RxBDReady <= 1'b0;
|
|
else
|
|
if(RxEn & RxEn_q & RxBDRead)
|
|
// RxBDReady is sampled only once at the beginning
|
|
RxBDReady <= ram_do[15];
|
|
end // always @ (posedge WB_CLK_I or posedge Reset)
|
|
|
|
// Indicate we just read the RX buffer descriptor and that RxBDReady is
|
|
// valid.
|
|
reg rx_just_read_bd;
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
|
if(Reset)
|
|
rx_just_read_bd <= 0;
|
|
else if (rx_just_read_bd)
|
|
rx_just_read_bd <= 0;
|
|
else
|
|
rx_just_read_bd <= (RxEn & RxEn_q & RxBDRead);
|
|
|
|
// Signal to indicate we've checked and the RxBD we want to use is not free
|
|
reg rx_waiting_for_bd_to_become_free;
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
|
if(Reset)
|
|
rx_waiting_for_bd_to_become_free <= 0;
|
|
else if (rx_just_read_bd & !RxBDReady)
|
|
// Assert if we read the BD and it's not cool
|
|
rx_waiting_for_bd_to_become_free <= 1;
|
|
else if (RxBDOK)
|
|
rx_waiting_for_bd_to_become_free <= 0;
|
|
|
|
|
|
|
|
// Latching Rx buffer descriptor status
|
|
// Data is avaliable one cycle after the access is started (at that time
|
|
// signal RxEn is not active)
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
RxStatus <= 2'h0;
|
|
else
|
|
if(RxEn & RxEn_q & RxBDRead)
|
|
RxStatus <= ram_do[14:13];
|
|
end
|
|
|
|
|
|
// RxBDOK generation
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
RxBDOK <= 1'b0;
|
|
else
|
|
if(rx_wb_writeback_finished | RxAbortSync2 & ~RxAbortSync3 |
|
|
~r_RxEn & r_RxEn_q)
|
|
RxBDOK <= 1'b0;
|
|
else
|
|
if(RxBDReady)
|
|
RxBDOK <= 1'b1;
|
|
end
|
|
|
|
// Reading Rx BD pointer
|
|
assign StartRxPointerRead = RxBDRead & RxBDReady;
|
|
|
|
// Reading Tx BD Pointer
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
RxPointerRead <= 1'b0;
|
|
else
|
|
if(StartRxPointerRead)
|
|
RxPointerRead <= 1'b1;
|
|
else
|
|
if(RxEn & RxEn_q)
|
|
RxPointerRead <= 1'b0;
|
|
end
|
|
|
|
|
|
//Latching Rx buffer pointer from buffer descriptor;
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
RxPointerMSB <= 30'h0;
|
|
else
|
|
if(RxEn & RxEn_q & RxPointerRead)
|
|
RxPointerMSB <= ram_do[31:2];
|
|
else
|
|
if(MasterWbRX & m_wb_ack_i)
|
|
// Word access (always word access. m_wb_sel_o are used for
|
|
// selecting bytes)
|
|
RxPointerMSB <= RxPointerMSB + 1'b1;
|
|
end
|
|
|
|
|
|
//Latching last addresses from buffer descriptor (used as byte-half-word
|
|
// indicator);
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
RxPointerLSB_rst[1:0] <= 0;
|
|
else
|
|
if(MasterWbRX & m_wb_ack_i)
|
|
// After first write all RxByteSel are active
|
|
RxPointerLSB_rst[1:0] <= 0;
|
|
else
|
|
if(RxEn & RxEn_q & RxPointerRead)
|
|
RxPointerLSB_rst[1:0] <= ram_do[1:0];
|
|
end
|
|
|
|
|
|
always @ (RxPointerLSB_rst)
|
|
begin
|
|
case(RxPointerLSB_rst[1:0]) // synopsys parallel_case
|
|
2'h0 : RxByteSel[3:0] = 4'hf;
|
|
2'h1 : RxByteSel[3:0] = 4'h7;
|
|
2'h2 : RxByteSel[3:0] = 4'h3;
|
|
2'h3 : RxByteSel[3:0] = 4'h1;
|
|
endcase
|
|
end
|
|
|
|
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
RxEn_needed <= 1'b0;
|
|
else
|
|
if(/*~RxReady &*/ r_RxEn & WbEn & ~WbEn_q)
|
|
RxEn_needed <= 1'b1;
|
|
else
|
|
if(RxPointerRead & RxEn & RxEn_q)
|
|
RxEn_needed <= 1'b0;
|
|
end
|
|
|
|
|
|
// Reception status is written back to the buffer descriptor after the end
|
|
// of frame is detected.
|
|
assign RxStatusWrite = rx_wb_writeback_finished & RxEn & RxEn_q;
|
|
|
|
reg RxEnableWindow;
|
|
|
|
// Indicating that last byte is being reveived
|
|
always @ (posedge MRxClk or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
LastByteIn <= 1'b0;
|
|
else
|
|
if(ShiftWillEnd & (&RxByteCnt) | RxAbort)
|
|
LastByteIn <= 1'b0;
|
|
else
|
|
if(RxValid /*& RxReady*/& RxEndFrm & ~(&RxByteCnt) & RxEnableWindow)
|
|
LastByteIn <= 1'b1;
|
|
end
|
|
|
|
assign StartShiftWillEnd = LastByteIn | RxValid & RxEndFrm & (&RxByteCnt) &
|
|
RxEnableWindow;
|
|
|
|
// Indicating that data reception will end
|
|
always @ (posedge MRxClk or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
ShiftWillEnd <= 1'b0;
|
|
else
|
|
if(ShiftEnded_rck | RxAbort)
|
|
ShiftWillEnd <= 1'b0;
|
|
else
|
|
if(StartShiftWillEnd)
|
|
ShiftWillEnd <= 1'b1;
|
|
end
|
|
|
|
// Receive byte counter
|
|
always @ (posedge MRxClk or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
RxByteCnt <= 2'h0;
|
|
else
|
|
if(ShiftEnded_rck | RxAbort)
|
|
RxByteCnt <= 2'h0;
|
|
else
|
|
if(RxValid & RxStartFrm /*& RxReady*/)
|
|
case(RxPointerLSB_rst) // synopsys parallel_case
|
|
2'h0 : RxByteCnt <= 2'h1;
|
|
2'h1 : RxByteCnt <= 2'h2;
|
|
2'h2 : RxByteCnt <= 2'h3;
|
|
2'h3 : RxByteCnt <= 2'h0;
|
|
endcase
|
|
else
|
|
if(RxValid & RxEnableWindow /*& RxReady*/ | LastByteIn)
|
|
RxByteCnt <= RxByteCnt + 1'b1;
|
|
end
|
|
|
|
|
|
// Indicates how many bytes are valid within the last word
|
|
always @ (posedge MRxClk or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
RxValidBytes <= 2'h1;
|
|
else
|
|
if(RxValid & RxStartFrm)
|
|
case(RxPointerLSB_rst) // synopsys parallel_case
|
|
2'h0 : RxValidBytes <= 2'h1;
|
|
2'h1 : RxValidBytes <= 2'h2;
|
|
2'h2 : RxValidBytes <= 2'h3;
|
|
2'h3 : RxValidBytes <= 2'h0;
|
|
endcase
|
|
else
|
|
if(RxValid & ~LastByteIn & ~RxStartFrm & RxEnableWindow)
|
|
RxValidBytes <= RxValidBytes + 1'b1;
|
|
end
|
|
|
|
|
|
always @ (posedge MRxClk or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
RxDataLatched1 <= 24'h0;
|
|
else
|
|
if(RxValid /*& RxReady*/ & ~LastByteIn)
|
|
if(RxStartFrm)
|
|
begin
|
|
case(RxPointerLSB_rst) // synopsys parallel_case
|
|
// Big Endian Byte Ordering
|
|
2'h0: RxDataLatched1[31:24] <= RxData;
|
|
2'h1: RxDataLatched1[23:16] <= RxData;
|
|
2'h2: RxDataLatched1[15:8] <= RxData;
|
|
2'h3: RxDataLatched1 <= RxDataLatched1;
|
|
endcase
|
|
end
|
|
else if (RxEnableWindow)
|
|
begin
|
|
case(RxByteCnt) // synopsys parallel_case
|
|
// Big Endian Byte Ordering
|
|
2'h0: RxDataLatched1[31:24] <= RxData;
|
|
2'h1: RxDataLatched1[23:16] <= RxData;
|
|
2'h2: RxDataLatched1[15:8] <= RxData;
|
|
2'h3: RxDataLatched1 <= RxDataLatched1;
|
|
endcase
|
|
end
|
|
end
|
|
|
|
wire SetWriteRxDataToFifo;
|
|
|
|
// Assembling data that will be written to the rx_fifo
|
|
always @ (posedge MRxClk or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
RxDataLatched2 <= 32'h0;
|
|
else
|
|
if(SetWriteRxDataToFifo & ~ShiftWillEnd)
|
|
// Big Endian Byte Ordering
|
|
RxDataLatched2 <= {RxDataLatched1[31:8], RxData};
|
|
else
|
|
if(SetWriteRxDataToFifo & ShiftWillEnd)
|
|
case(RxValidBytes) // synopsys parallel_case
|
|
// Big Endian Byte Ordering
|
|
0 : RxDataLatched2 <= {RxDataLatched1[31:8], RxData};
|
|
1 : RxDataLatched2 <= {RxDataLatched1[31:24], 24'h0};
|
|
2 : RxDataLatched2 <= {RxDataLatched1[31:16], 16'h0};
|
|
3 : RxDataLatched2 <= {RxDataLatched1[31:8], 8'h0};
|
|
endcase
|
|
end
|
|
|
|
|
|
reg WriteRxDataToFifoSync1;
|
|
reg WriteRxDataToFifoSync2;
|
|
reg WriteRxDataToFifoSync3;
|
|
|
|
|
|
// Indicating start of the reception process
|
|
assign SetWriteRxDataToFifo = (RxValid &/* RxReady &*/ ~RxStartFrm &
|
|
RxEnableWindow & (&RxByteCnt)) |
|
|
(RxValid &/* RxReady &*/ RxStartFrm &
|
|
(&RxPointerLSB_rst)) |
|
|
(ShiftWillEnd & LastByteIn & (&RxByteCnt));
|
|
|
|
always @ (posedge MRxClk or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
WriteRxDataToFifo <= 1'b0;
|
|
else
|
|
if(SetWriteRxDataToFifo & ~RxAbort)
|
|
WriteRxDataToFifo <= 1'b1;
|
|
else
|
|
if(WriteRxDataToFifoSync2 | RxAbort)
|
|
WriteRxDataToFifo <= 1'b0;
|
|
end
|
|
|
|
|
|
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
WriteRxDataToFifoSync1 <= 1'b0;
|
|
else
|
|
if(WriteRxDataToFifo)
|
|
WriteRxDataToFifoSync1 <= 1'b1;
|
|
else
|
|
WriteRxDataToFifoSync1 <= 1'b0;
|
|
end
|
|
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
WriteRxDataToFifoSync2 <= 1'b0;
|
|
else
|
|
WriteRxDataToFifoSync2 <= WriteRxDataToFifoSync1;
|
|
end
|
|
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
WriteRxDataToFifoSync3 <= 1'b0;
|
|
else
|
|
WriteRxDataToFifoSync3 <= WriteRxDataToFifoSync2;
|
|
end
|
|
|
|
wire WriteRxDataToFifo_wb;
|
|
assign WriteRxDataToFifo_wb = WriteRxDataToFifoSync2 &
|
|
~WriteRxDataToFifoSync3;
|
|
// Receive fifo selection register - JB
|
|
reg [3:0] rx_shift_ended_wb_shr;
|
|
reg rx_ethside_fifo_sel;
|
|
reg rx_wbside_fifo_sel;
|
|
|
|
// Shift in this - our detection of end of data RX
|
|
always @(posedge WB_CLK_I)
|
|
rx_shift_ended_wb_shr <= {rx_shift_ended_wb_shr[2:0],
|
|
ShiftEndedSync1 & ~ShiftEndedSync2};
|
|
|
|
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
|
if(Reset)
|
|
rx_ethside_fifo_sel <= 0;
|
|
else
|
|
if(rx_shift_ended_wb_shr[3:2] == 2'b01)
|
|
// Switch over whenever we've finished receiving last frame's data
|
|
rx_ethside_fifo_sel <= ~rx_ethside_fifo_sel;
|
|
|
|
// Wishbone side looks at other FIFO when we write back the status of this
|
|
// received frame
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
|
if(Reset)
|
|
rx_wbside_fifo_sel <= 0;
|
|
else
|
|
if(rx_wb_writeback_finished & RxEn & RxEn_q)
|
|
// Switch over whenever we've finished receiving last frame's data
|
|
rx_wbside_fifo_sel <= ~rx_wbside_fifo_sel;
|
|
|
|
reg LatchedRxStartFrm;
|
|
reg SyncRxStartFrm;
|
|
reg SyncRxStartFrm_q;
|
|
reg SyncRxStartFrm_q2;
|
|
wire RxFifoReset;
|
|
|
|
always @ (posedge MRxClk or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
LatchedRxStartFrm <= 0;
|
|
else
|
|
if(RxStartFrm & ~SyncRxStartFrm_q)
|
|
LatchedRxStartFrm <= 1;
|
|
else
|
|
if(SyncRxStartFrm_q)
|
|
LatchedRxStartFrm <= 0;
|
|
end
|
|
|
|
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
SyncRxStartFrm <= 0;
|
|
else
|
|
if(LatchedRxStartFrm)
|
|
SyncRxStartFrm <= 1;
|
|
else
|
|
SyncRxStartFrm <= 0;
|
|
end
|
|
|
|
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
SyncRxStartFrm_q <= 0;
|
|
else
|
|
SyncRxStartFrm_q <= SyncRxStartFrm;
|
|
end
|
|
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
SyncRxStartFrm_q2 <= 0;
|
|
else
|
|
SyncRxStartFrm_q2 <= SyncRxStartFrm_q;
|
|
end
|
|
wire rx_startfrm_wb;
|
|
assign rx_startfrm_wb = SyncRxStartFrm_q & ~SyncRxStartFrm_q2;
|
|
|
|
|
|
assign RxFifoReset = rx_startfrm_wb;
|
|
|
|
|
|
wire [31:0] rx_fifo0_data_out;
|
|
wire rx_fifo0_write;
|
|
wire rx_fifo0_read;
|
|
wire rx_fifo0_clear;
|
|
wire rx_fifo0_full;
|
|
wire rx_fifo0_afull;
|
|
wire rx_fifo0_empty;
|
|
wire rx_fifo0_aempty;
|
|
|
|
|
|
wire [31:0] rx_fifo1_data_out;
|
|
wire rx_fifo1_write;
|
|
wire rx_fifo1_read;
|
|
wire rx_fifo1_clear;
|
|
wire rx_fifo1_full;
|
|
wire rx_fifo1_afull;
|
|
wire rx_fifo1_empty;
|
|
wire rx_fifo1_aempty;
|
|
|
|
wire [`ETH_RX_FIFO_CNT_WIDTH-1:0] rx_fifo0_cnt;
|
|
wire [`ETH_RX_FIFO_CNT_WIDTH-1:0] rx_fifo1_cnt;
|
|
|
|
// RX FIFO buffer 0 controls
|
|
assign rx_fifo0_write = (!rx_ethside_fifo_sel) & WriteRxDataToFifo_wb &
|
|
~rx_fifo0_full;
|
|
|
|
assign rx_fifo0_read = (!rx_wbside_fifo_sel) & MasterWbRX & m_wb_ack_i &
|
|
~rx_fifo0_empty;
|
|
|
|
assign rx_fifo0_clear = (!rx_ethside_fifo_sel) & RxFifoReset;
|
|
|
|
// RX FIFO buffer 1 controls
|
|
assign rx_fifo1_write = (rx_ethside_fifo_sel) & WriteRxDataToFifo_wb &
|
|
~rx_fifo1_full;
|
|
|
|
assign rx_fifo1_read = (rx_wbside_fifo_sel) & MasterWbRX & m_wb_ack_i &
|
|
~rx_fifo1_empty;
|
|
|
|
assign rx_fifo1_clear = (rx_ethside_fifo_sel) & RxFifoReset;
|
|
|
|
eth_fifo #(
|
|
`ETH_RX_FIFO_DATA_WIDTH,
|
|
`ETH_RX_FIFO_DEPTH,
|
|
`ETH_RX_FIFO_CNT_WIDTH
|
|
)
|
|
rx_fifo0 (
|
|
.clk (WB_CLK_I ),
|
|
.reset (Reset ),
|
|
// Inputs
|
|
.data_in (RxDataLatched2 ),
|
|
.write (rx_fifo0_write ),
|
|
.read (rx_fifo0_read ),
|
|
.clear (rx_fifo0_clear ),
|
|
// Outputs
|
|
.data_out (rx_fifo0_data_out),
|
|
.full (rx_fifo0_full ),
|
|
.almost_full (),
|
|
.almost_empty (rx_fifo0_aempty ),
|
|
.empty (rx_fifo0_empty ),
|
|
.cnt (rx_fifo0_cnt )
|
|
);
|
|
|
|
eth_fifo #(
|
|
`ETH_RX_FIFO_DATA_WIDTH,
|
|
`ETH_RX_FIFO_DEPTH,
|
|
`ETH_RX_FIFO_CNT_WIDTH
|
|
)
|
|
rx_fifo1 (
|
|
.clk (WB_CLK_I ),
|
|
.reset (Reset ),
|
|
// Inputs
|
|
.data_in (RxDataLatched2 ),
|
|
.write (rx_fifo1_write ),
|
|
.read (rx_fifo1_read ),
|
|
.clear (rx_fifo1_clear ),
|
|
// Outputs
|
|
.data_out (rx_fifo1_data_out),
|
|
.full (rx_fifo1_full ),
|
|
.almost_full (),
|
|
.almost_empty (rx_fifo1_aempty ),
|
|
.empty (rx_fifo1_empty ),
|
|
.cnt (rx_fifo1_cnt )
|
|
);
|
|
|
|
assign m_wb_dat_o = rx_wbside_fifo_sel ?
|
|
rx_fifo1_data_out : rx_fifo0_data_out;
|
|
assign rxfifo_cnt = rx_wbside_fifo_sel ?
|
|
rx_fifo1_cnt : rx_fifo0_cnt;
|
|
|
|
assign RxBufferAlmostEmpty = rx_wbside_fifo_sel ?
|
|
rx_fifo1_aempty : rx_fifo0_aempty;
|
|
|
|
assign RxBufferEmpty = rx_wbside_fifo_sel ?
|
|
rx_fifo1_empty : rx_fifo0_empty;
|
|
|
|
assign RxBufferFull = rx_wbside_fifo_sel ?
|
|
rx_fifo1_full : rx_fifo0_full;
|
|
|
|
|
|
|
|
|
|
|
|
wire write_rx_data_to_memory_wait;
|
|
assign write_rx_data_to_memory_wait = !RxBDOK | RxPointerRead;
|
|
wire write_rx_data_to_memory_go;
|
|
|
|
`ifdef ETH_RX_BURST_EN
|
|
assign enough_data_in_rxfifo_for_burst = rxfifo_cnt>=(`ETH_BURST_LENGTH);
|
|
assign enough_data_in_rxfifo_for_burst_plus1 = rxfifo_cnt>(`ETH_BURST_LENGTH - 1);
|
|
// While receiving, don't flog the bus too hard, only write out when
|
|
// we can burst. But when finishing keep going until we've emptied the fifo
|
|
assign write_rx_data_to_memory_go =
|
|
RxEnableWindow & (rx_wbside_fifo_sel == rx_ethside_fifo_sel) ?
|
|
(rxfifo_cnt>(`ETH_BURST_LENGTH)+2) |
|
|
(|rx_burst_cnt) : ~RxBufferEmpty;
|
|
|
|
`else
|
|
assign enough_data_in_rxfifo_for_burst = rxfifo_cnt>=`ETH_BURST_LENGTH;
|
|
assign enough_data_in_rxfifo_for_burst_plus1 = rxfifo_cnt>`ETH_BURST_LENGTH;
|
|
assign write_rx_data_to_memory_go = ~RxBufferEmpty;
|
|
`endif // !`ifdef ETH_RX_BURST_EN
|
|
|
|
assign WriteRxDataToMemory = write_rx_data_to_memory_go & !write_rx_data_to_memory_wait;
|
|
|
|
assign rx_burst = rx_burst_en & WriteRxDataToMemory;
|
|
|
|
|
|
// Generation of the end-of-frame signal
|
|
always @ (posedge MRxClk or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
ShiftEnded_rck <= 1'b0;
|
|
else
|
|
if(~RxAbort & SetWriteRxDataToFifo & StartShiftWillEnd)
|
|
ShiftEnded_rck <= 1'b1;
|
|
else
|
|
if(RxAbort | ShiftEndedSync_c1 & ShiftEndedSync_c2)
|
|
ShiftEnded_rck <= 1'b0;
|
|
end
|
|
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
ShiftEndedSync1 <= 1'b0;
|
|
else
|
|
ShiftEndedSync1 <= ShiftEnded_rck;
|
|
end
|
|
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
ShiftEndedSync2 <= 1'b0;
|
|
else
|
|
ShiftEndedSync2 <= ShiftEndedSync1;
|
|
end
|
|
|
|
// indicate end of wishbone RX is coming up
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
|
if(Reset)
|
|
rx_wb_last_writes <= 1'b0;
|
|
else if (!rx_wb_last_writes)
|
|
rx_wb_last_writes <= ShiftEndedSync1 & ~ShiftEndedSync2;
|
|
else if (rx_wb_writeback_finished & RxEn & RxEn_q)
|
|
rx_wb_last_writes <= 0;
|
|
|
|
// Pulse indicating last of RX data has been written out
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
|
if(Reset)
|
|
rx_wb_writeback_finished <= 0;
|
|
else if (rx_wb_writeback_finished & RxEn & RxEn_q)
|
|
rx_wb_writeback_finished <= 0;
|
|
else
|
|
rx_wb_writeback_finished <= rx_wb_last_writes & RxBufferEmpty &
|
|
!WriteRxDataToFifo_wb;
|
|
|
|
|
|
always @ (posedge MRxClk or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
ShiftEndedSync_c1 <= 1'b0;
|
|
else
|
|
ShiftEndedSync_c1 <= ShiftEndedSync2;
|
|
end
|
|
|
|
always @ (posedge MRxClk or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
ShiftEndedSync_c2 <= 1'b0;
|
|
else
|
|
ShiftEndedSync_c2 <= ShiftEndedSync_c1;
|
|
end
|
|
|
|
// Generation of the end-of-frame signal
|
|
always @ (posedge MRxClk or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
RxEnableWindow <= 1'b0;
|
|
else
|
|
if(RxStartFrm)
|
|
RxEnableWindow <= 1'b1;
|
|
else
|
|
if(RxEndFrm | RxAbort)
|
|
RxEnableWindow <= 1'b0;
|
|
end
|
|
|
|
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
RxAbortSync1 <= 1'b0;
|
|
else
|
|
RxAbortSync1 <= RxAbortLatched;
|
|
end
|
|
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
RxAbortSync2 <= 1'b0;
|
|
else
|
|
RxAbortSync2 <= RxAbortSync1;
|
|
end
|
|
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
RxAbortSync3 <= 1'b0;
|
|
else
|
|
RxAbortSync3 <= RxAbortSync2;
|
|
end
|
|
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
RxAbortSync4 <= 1'b0;
|
|
else
|
|
RxAbortSync4 <= RxAbortSync3;
|
|
end
|
|
|
|
always @ (posedge MRxClk or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
RxAbortSyncb1 <= 1'b0;
|
|
else
|
|
RxAbortSyncb1 <= RxAbortSync2;
|
|
end
|
|
|
|
always @ (posedge MRxClk or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
RxAbortSyncb2 <= 1'b0;
|
|
else
|
|
RxAbortSyncb2 <= RxAbortSyncb1;
|
|
end
|
|
|
|
|
|
always @ (posedge MRxClk or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
RxAbortLatched <= 1'b0;
|
|
else
|
|
if(RxAbortSyncb2)
|
|
RxAbortLatched <= 1'b0;
|
|
else
|
|
if(RxAbort)
|
|
RxAbortLatched <= 1'b1;
|
|
end
|
|
|
|
|
|
always @ (posedge MRxClk or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
LatchedRxLength[15:0] <= 16'h0;
|
|
else
|
|
if(LoadRxStatus)
|
|
LatchedRxLength[15:0] <= RxLength[15:0];
|
|
end
|
|
|
|
|
|
assign RxStatusIn = {ReceivedPauseFrm, AddressMiss, RxOverrun, InvalidSymbol, DribbleNibble, ReceivedPacketTooBig, ShortFrame, LatchedCrcError, RxLateCollision};
|
|
|
|
always @ (posedge MRxClk or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
RxStatusInLatched <= 'h0;
|
|
else
|
|
if(LoadRxStatus)
|
|
RxStatusInLatched <= RxStatusIn;
|
|
end
|
|
|
|
|
|
// Rx overrun
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
RxOverrun <= 1'b0;
|
|
else
|
|
if(RxStatusWrite)
|
|
RxOverrun <= 1'b0;
|
|
else
|
|
if(RxBufferFull & WriteRxDataToFifo_wb)
|
|
RxOverrun <= 1'b1;
|
|
end
|
|
|
|
|
|
|
|
wire TxError;
|
|
assign TxError = TxUnderRun | RetryLimit | LateCollLatched | CarrierSenseLost;
|
|
|
|
wire RxError;
|
|
|
|
// ShortFrame (RxStatusInLatched[2]) can not set an error because short
|
|
// frames are aborted when signal r_RecSmall is set to 0 in MODER register.
|
|
// AddressMiss is identifying that a frame was received because of the
|
|
// promiscous mode and is not an error
|
|
assign RxError = (|RxStatusInLatched[6:3]) | (|RxStatusInLatched[1:0]);
|
|
|
|
|
|
|
|
reg RxStatusWriteLatched;
|
|
reg RxStatusWriteLatched_sync1;
|
|
reg RxStatusWriteLatched_sync2;
|
|
reg RxStatusWriteLatched_syncb1;
|
|
reg RxStatusWriteLatched_syncb2;
|
|
|
|
|
|
// Latching and synchronizing RxStatusWrite signal. This signal is used for
|
|
// clearing the ReceivedPauseFrm signal
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
RxStatusWriteLatched <= 1'b0;
|
|
else
|
|
if(RxStatusWriteLatched_syncb2)
|
|
RxStatusWriteLatched <= 1'b0;
|
|
else
|
|
if(RxStatusWrite)
|
|
RxStatusWriteLatched <= 1'b1;
|
|
end
|
|
|
|
|
|
always @ (posedge MRxClk or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
begin
|
|
RxStatusWriteLatched_sync1 <= 1'b0;
|
|
RxStatusWriteLatched_sync2 <= 1'b0;
|
|
end
|
|
else
|
|
begin
|
|
RxStatusWriteLatched_sync1 <= RxStatusWriteLatched;
|
|
RxStatusWriteLatched_sync2 <= RxStatusWriteLatched_sync1;
|
|
end
|
|
end
|
|
|
|
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
begin
|
|
RxStatusWriteLatched_syncb1 <= 1'b0;
|
|
RxStatusWriteLatched_syncb2 <= 1'b0;
|
|
end
|
|
else
|
|
begin
|
|
RxStatusWriteLatched_syncb1 <= RxStatusWriteLatched_sync2;
|
|
RxStatusWriteLatched_syncb2 <= RxStatusWriteLatched_syncb1;
|
|
end
|
|
end
|
|
|
|
|
|
|
|
// Tx Done Interrupt
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
TxB_IRQ <= 1'b0;
|
|
else
|
|
if(TxStatusWrite & TxIRQEn)
|
|
TxB_IRQ <= ~TxError;
|
|
else
|
|
TxB_IRQ <= 1'b0;
|
|
end
|
|
|
|
|
|
// Tx Error Interrupt
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
TxE_IRQ <= 1'b0;
|
|
else
|
|
if(TxStatusWrite & TxIRQEn)
|
|
TxE_IRQ <= TxError;
|
|
else
|
|
TxE_IRQ <= 1'b0;
|
|
end
|
|
|
|
|
|
// Rx Done Interrupt
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
RxB_IRQ <= 1'b0;
|
|
else
|
|
if(RxStatusWrite & RxIRQEn & ReceivedPacketGood &
|
|
(~ReceivedPauseFrm | ReceivedPauseFrm & r_PassAll & (~r_RxFlow)))
|
|
RxB_IRQ <= (~RxError);
|
|
else
|
|
RxB_IRQ <= 1'b0;
|
|
end
|
|
|
|
|
|
// Rx Error Interrupt
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
RxE_IRQ <= 1'b0;
|
|
else
|
|
if(RxStatusWrite & RxIRQEn & (~ReceivedPauseFrm | ReceivedPauseFrm
|
|
& r_PassAll & (~r_RxFlow)))
|
|
RxE_IRQ <= RxError;
|
|
else
|
|
RxE_IRQ <= 1'b0;
|
|
end
|
|
|
|
// Set this high when we started receiving another packet while the wishbone
|
|
// side was still writing out the last one. This makes sure we check at the
|
|
// right time if the next buffer descriptor is free.
|
|
reg rxstartfrm_occurred;
|
|
always @ (posedge WB_CLK_I)
|
|
if (Reset)
|
|
rxstartfrm_occurred <= 0;
|
|
else if (rx_just_read_bd)
|
|
rxstartfrm_occurred <= 0;
|
|
else if (((rx_ethside_fifo_sel != rx_wbside_fifo_sel) | StartRxBDRead |
|
|
RxBDRead) & rx_startfrm_wb)
|
|
rxstartfrm_occurred <= 1;
|
|
|
|
|
|
|
|
reg busy_wb;
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
|
if(Reset)
|
|
busy_wb <= 0;
|
|
else if (busy_wb)
|
|
busy_wb <= 0;
|
|
else if
|
|
// Indicate busy if either:
|
|
// a) RX is idle and we get a start frame and current BD indicates not
|
|
// ready.
|
|
// b) RX is already receiving another packet and we got a startframe,
|
|
// indicated by rx_startfrm_occurred, and we then read the BD and
|
|
// it says it's not ready.
|
|
// This actually may not work since it's in the MII RX clock domain.
|
|
((rx_ethside_fifo_sel == rx_wbside_fifo_sel) &
|
|
((rxstartfrm_occurred & rx_just_read_bd & ~RxBDReady) |
|
|
(!rxstartfrm_occurred & !StartRxBDRead & !RxBDRead & rx_startfrm_wb &
|
|
rx_waiting_for_bd_to_become_free))
|
|
)
|
|
busy_wb <= 1;
|
|
|
|
|
|
assign Busy_IRQ = busy_wb;
|
|
|
|
always @(posedge Busy_IRQ)
|
|
$display("(%t)(%m) Ethernet MAC BUSY signal asserted", $time);
|
|
|
|
|
|
// Assign the debug output
|
|
`ifdef WISHBONE_DEBUG
|
|
// Top byte, burst progress counters
|
|
assign dbg_dat0[31] = 0;
|
|
assign dbg_dat0[30] = 0;
|
|
assign dbg_dat0[29:28] = rx_burst_cnt;
|
|
assign dbg_dat0[27] = 0;
|
|
assign dbg_dat0[26] = 0;
|
|
assign dbg_dat0[25:24] = tx_burst_cnt;
|
|
|
|
// Third byte
|
|
assign dbg_dat0[23] = 0;
|
|
assign dbg_dat0[22] = 0;
|
|
assign dbg_dat0[21] = rx_burst;
|
|
assign dbg_dat0[20] = rx_burst_en;
|
|
assign dbg_dat0[19] = 0;
|
|
assign dbg_dat0[18] = 0;
|
|
assign dbg_dat0[17] = tx_burst;
|
|
assign dbg_dat0[16] = tx_burst_en;
|
|
// Second byte - TxBDAddress - or TX BD address pointer
|
|
assign dbg_dat0[15:8] = { 1'b0, TxBDAddress};
|
|
// Bottom byte - FSM controlling vector
|
|
assign dbg_dat0[7:0] = {MasterWbTX,MasterWbRX,
|
|
ReadTxDataFromMemory_2,WriteRxDataToMemory,
|
|
MasterAccessFinished,cyc_cleared,
|
|
tx_burst,rx_burst};
|
|
|
|
`endif
|
|
|
|
|
|
|
|
endmodule
|
|
|
No newline at end of file
|
No newline at end of file
|
