| Line 191... |
Line 191... |
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// state machine variable
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// state machine variable
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reg [17:0] c_state; // synopsys enum_state
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reg [17:0] c_state; // synopsys enum_state
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reg [4:0] slave_state;
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reg [4:0] slave_state;
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// A counter to indicate a too-long wait has occurred for the next set
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// of clocks for the read, and in fact it's likely the master has simply
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// released SCL and wants to issue a stop.
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reg [3:0] slave_read_timeout_cnt;
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wire slave_read_timeout;
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//
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//
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// module body
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// module body
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//
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//
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// whenever the slave is not ready it can delay the cycle by pulling SCL low
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// whenever the slave is not ready it can delay the cycle by pulling SCL low
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// delay scl_oen
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// delay scl_oen
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always @(posedge clk)
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always @(posedge clk)
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dscl_oen <= scl_oen;
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dscl_oen <= scl_oen;
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// slave_wait is asserted when master wants to drive SCL high, but the slave pulls it low
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// slave_wait is asserted when master wants to drive SCL high, but the
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// slave pulls it low.
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// slave_wait remains asserted until the slave releases SCL
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// slave_wait remains asserted until the slave releases SCL
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always @(posedge clk or negedge nReset)
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always @(posedge clk or negedge nReset)
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if (!nReset) slave_wait <= 1'b0;
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if (!nReset)
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else slave_wait <= (scl_oen & ~dscl_oen & ~sSCL) | (slave_wait & ~sSCL);
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slave_wait <= 1'b0;
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else
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slave_wait <= (scl_oen & ~dscl_oen & ~sSCL) |
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(slave_wait & ~sSCL) ;
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// master drives SCL high, but another master pulls it low
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// master drives SCL high, but another master pulls it low
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// master start counting down its low cycle now (clock synchronization)
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// master start counting down its low cycle now (clock synchronization)
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wire scl_sync = dSCL & ~sSCL & scl_oen;
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wire scl_sync = dSCL & ~sSCL & scl_oen;
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| Line 234... |
Line 246... |
begin
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begin
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cnt <= cnt - 16'h1;
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cnt <= cnt - 16'h1;
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clk_en <= 1'b0;
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clk_en <= 1'b0;
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end
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end
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// generate bus status controller
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// generate bus status controller
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// capture SDA and SCL
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// capture SDA and SCL
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// reduce metastability risk
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// reduce metastability risk
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always @(posedge clk or negedge nReset)
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always @(posedge clk or negedge nReset)
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| Line 629... |
Line 640... |
slave_adr_received <= 1'b0;
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slave_adr_received <= 1'b0;
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slave_act <= 1'b0;
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slave_act <= 1'b0;
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end
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end
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end
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end
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parameter [4:0] slave_idle = 5'b0_0000;
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parameter [4:0] slave_idle = 5'b0_0000;
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parameter [4:0] slave_wr = 5'b0_0001;
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parameter [4:0] slave_wr = 5'b0_0001;
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parameter [4:0] slave_wr_a = 5'b0_0010;
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parameter [4:0] slave_wr_a = 5'b0_0010;
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parameter [4:0] slave_rd = 5'b0_0100;
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parameter [4:0] slave_rd = 5'b0_0100;
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parameter [4:0] slave_rd_a = 5'b0_1000;
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parameter [4:0] slave_rd_a = 5'b0_1000;
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parameter [4:0] slave_wait_next_cmd_1 = 5'b1_0000;
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parameter [4:0] slave_wait_next_cmd_1 = 5'b1_0000;
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parameter [4:0] slave_wait_next_cmd_2 = 5'b1_0001;
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parameter [4:0] slave_wait_next_cmd_2 = 5'b1_0001;
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// Slave timeout counter during read
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always @(posedge clk or negedge nReset)
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if (~nReset)
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slave_read_timeout_cnt <= 0;
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else if (rst)
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slave_read_timeout_cnt <= 0;
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else if (slave_state==slave_wr)
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slave_read_timeout_cnt <= 0;
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else if (slave_state==slave_wr_a && sSCL && cnt==1)
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slave_read_timeout_cnt <= slave_read_timeout_cnt + 1;
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assign slave_read_timeout = (&slave_read_timeout_cnt) & cnt==1;
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always @(posedge clk or negedge nReset)
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always @(posedge clk or negedge nReset)
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if (!nReset)
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if (!nReset)
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begin
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begin
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slave_state <= slave_idle;
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slave_state <= slave_idle;
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cmd_slave_ack <= 1'b0;
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cmd_slave_ack <= 1'b0;
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| Line 693... |
Line 716... |
begin
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begin
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if (~sSCL & dSCL) begin //SCL FALLING EDGE
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if (~sSCL & dSCL) begin //SCL FALLING EDGE
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cmd_slave_ack <= 1'b1;
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cmd_slave_ack <= 1'b1;
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slave_state <= slave_wait_next_cmd_1;
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slave_state <= slave_wait_next_cmd_1;
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end
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end
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// Timeout! Go back to idle, release SDA
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else if(slave_read_timeout) begin
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slave_state <= slave_idle;
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sda_oen_slave <= 1;
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end
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end
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end
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slave_wait_next_cmd_1:
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slave_wait_next_cmd_1:
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slave_state <= slave_wait_next_cmd_2;
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slave_state <= slave_wait_next_cmd_2;
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