URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [include/] [or1200_defines.v] - Diff between revs 435 and 462

Rev 435	Rev 462
Line 387...	Line 387...
//`define OR1200_DIV_SERIAL	//`define OR1200_DIV_SERIAL

`//`	`//`
`// Implement HW Single Precision FPU`	`// Implement HW Single Precision FPU`
`//`	`//`
//`define OR1200_FPU_IMPLEMENTED	`define OR1200_FPU_IMPLEMENTED
`//`

`//`	`//`
`// Clock ratio RISC clock versus WB clock`	`// Clock ratio RISC clock versus WB clock`
`//`	`//`
`// If you plan to run WB:RISC clock fixed to 1:1, disable`	`// If you plan to run WB:RISC clock fixed to 1:1, disable`