| Line 159... |
Line 159... |
//
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//
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// Size/type of insn/data cache if implemented
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// Size/type of insn/data cache if implemented
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// (consider available FPGA memory resources)
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// (consider available FPGA memory resources)
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//
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//
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//`define OR1200_IC_1W_512B
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//`define OR1200_IC_1W_512B
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//`define OR1200_IC_1W_4KB
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`define OR1200_IC_1W_4KB
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//`define OR1200_IC_1W_8KB
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//`define OR1200_IC_1W_8KB
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`define OR1200_IC_1W_16KB
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//`define OR1200_IC_1W_16KB
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//`define OR1200_DC_1W_4KB
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//`define OR1200_IC_1W_32KB
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`define OR1200_DC_1W_4KB
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//`define OR1200_DC_1W_8KB
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//`define OR1200_DC_1W_8KB
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`define OR1200_DC_1W_16KB
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//`define OR1200_DC_1W_16KB
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//`define OR1200_DC_1W_32KB
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`endif
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`endif
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//////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////
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| Line 1219... |
Line 1221... |
/////////////////////////////////////////////////
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/////////////////////////////////////////////////
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//
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//
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// Insn cache (IC)
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// Insn cache (IC)
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//
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//
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// 3 for 8 bytes, 4 for 16 bytes etc
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// 4 for 16 byte line, 5 for 32 byte lines.
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`ifdef OR1200_IC_1W_32KB
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`define OR1200_ICLS 5
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`else
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`define OR1200_ICLS 4
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`define OR1200_ICLS 4
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`endif
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//
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//
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// IC configurations
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// IC configurations
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//
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//
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`ifdef OR1200_IC_1W_512B
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`ifdef OR1200_IC_1W_512B
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| Line 1257... |
Line 1263... |
`define OR1200_ICINDXH `OR1200_ICSIZE-1 // 13
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`define OR1200_ICINDXH `OR1200_ICSIZE-1 // 13
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`define OR1200_ICTAGL `OR1200_ICINDXH+1 // 14
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`define OR1200_ICTAGL `OR1200_ICINDXH+1 // 14
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`define OR1200_ICTAG `OR1200_ICSIZE-`OR1200_ICLS // 10
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`define OR1200_ICTAG `OR1200_ICSIZE-`OR1200_ICLS // 10
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`define OR1200_ICTAG_W 19
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`define OR1200_ICTAG_W 19
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`endif
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`endif
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`ifdef OR1200_IC_1W_32KB
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`define OR1200_ICSIZE 15 // 32768
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`define OR1200_ICINDX `OR1200_ICSIZE-2 // 13
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`define OR1200_ICINDXH `OR1200_ICSIZE-1 // 14
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`define OR1200_ICTAGL `OR1200_ICINDXH+1 // 14
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`define OR1200_ICTAG `OR1200_ICSIZE-`OR1200_ICLS // 10
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`define OR1200_ICTAG_W 18
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`endif
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/////////////////////////////////////////////////
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/////////////////////////////////////////////////
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//
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//
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// Data cache (DC)
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// Data cache (DC)
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//
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//
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|
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// 3 for 8 bytes, 4 for 16 bytes etc
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// 4 for 16 bytes, 5 for 32 bytes
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`ifdef OR1200_DC_1W_32KB
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`define OR1200_DCLS 5
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`else
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`define OR1200_DCLS 4
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`define OR1200_DCLS 4
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`endif
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// Define to enable default behavior of cache as write through
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// Define to enable default behavior of cache as write through
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// Turning this off enabled write back statergy
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// Turning this off enabled write back statergy
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//
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//
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`define OR1200_DC_WRITETHROUGH
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`define OR1200_DC_WRITETHROUGH
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| Line 1313... |
Line 1331... |
`define OR1200_DCINDXH `OR1200_DCSIZE-1 // 13
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`define OR1200_DCINDXH `OR1200_DCSIZE-1 // 13
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`define OR1200_DCTAGL `OR1200_DCINDXH+1 // 14
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`define OR1200_DCTAGL `OR1200_DCINDXH+1 // 14
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`define OR1200_DCTAG `OR1200_DCSIZE-`OR1200_DCLS // 10
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`define OR1200_DCTAG `OR1200_DCSIZE-`OR1200_DCLS // 10
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`define OR1200_DCTAG_W 19
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`define OR1200_DCTAG_W 19
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`endif
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`endif
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`ifdef OR1200_DC_1W_32KB
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`define OR1200_DCSIZE 15 // 32768
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`define OR1200_DCINDX `OR1200_DCSIZE-2 // 13
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`define OR1200_DCINDXH `OR1200_DCSIZE-1 // 14
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`define OR1200_DCTAGL `OR1200_DCINDXH+1 // 15
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`define OR1200_DCTAG `OR1200_DCSIZE-`OR1200_DCLS // 10
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`define OR1200_DCTAG_W 18
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`endif
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/////////////////////////////////////////////////
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/////////////////////////////////////////////////
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//
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//
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// Store buffer (SB)
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// Store buffer (SB)
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