OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [include/] [or1200_defines.v] - Diff between revs 501 and 502

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 501 Rev 502
Line 297... Line 297...
// By default implementation of l.addc/l.addic
// By default implementation of l.addc/l.addic
// instructions is enabled in case you need them.
// instructions is enabled in case you need them.
// If you don't use them, then disable implementation
// If you don't use them, then disable implementation
// to save area.
// to save area.
//
//
//`define OR1200_IMPL_ADDC
`define OR1200_IMPL_ADDC
 
 
//
//
// Implement l.sub instruction
// Implement l.sub instruction
//
//
// By default implementation of l.sub instructions
// By default implementation of l.sub instructions
Line 319... Line 319...
// to be compliant with the simulator. However SR[CY]
// to be compliant with the simulator. However SR[CY]
// is explicitly only used by l.addc/l.addic/l.sub
// is explicitly only used by l.addc/l.addic/l.sub
// instructions and if these three insns are not
// instructions and if these three insns are not
// implemented there is not much point having SR[CY].
// implemented there is not much point having SR[CY].
//
//
//`define OR1200_IMPL_CY
`define OR1200_IMPL_CY
 
 
 
//
 
// Implement carry bit SR[OV]
 
//
 
// Compiler doesn't use this, but other code may like
 
// to.
 
//
 
`define OR1200_IMPL_OV
 
 
 
//
 
// Implement carry bit SR[OVE]
 
//
 
// Overflow interrupt indicator. When enabled, SR[OV] flag
 
// does not remain asserted after exception.
 
//
 
`define OR1200_IMPL_OVE
 
 
 
 
//
//
// Implement rotate in the ALU
// Implement rotate in the ALU
//
//
// At the time of writing this, or32
// At the time of writing this, or32
Line 823... Line 840...
`define OR1200_SR_DME  5
`define OR1200_SR_DME  5
`define OR1200_SR_IME  6
`define OR1200_SR_IME  6
`define OR1200_SR_LEE  7
`define OR1200_SR_LEE  7
`define OR1200_SR_CE   8
`define OR1200_SR_CE   8
`define OR1200_SR_F    9
`define OR1200_SR_F    9
`define OR1200_SR_CY   10       // Unused
`define OR1200_SR_CY   10       // Optional
`define OR1200_SR_OV   11       // Unused
`define OR1200_SR_OV   11       // Optional
`define OR1200_SR_OVE  12       // Unused
`define OR1200_SR_OVE  12       // Optional
`define OR1200_SR_DSX  13       // Unused
`define OR1200_SR_DSX  13       // Unused
`define OR1200_SR_EPH  14
`define OR1200_SR_EPH  14
`define OR1200_SR_FO   15
`define OR1200_SR_FO   15
`define OR1200_SR_TED  16
`define OR1200_SR_TED  16
`define OR1200_SR_CID  31:28    // Unimplemented
`define OR1200_SR_CID  31:28    // Unimplemented

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.