| Line 865... |
Line 865... |
//
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//
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// Debug Unit (DU)
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// Debug Unit (DU)
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//
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//
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// Define it if you want DU implemented
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// Define it if you want DU implemented
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`define OR1200_DU_IMPLEMENTED
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//`define OR1200_DU_IMPLEMENTED
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//
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//
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// Define if you want HW Breakpoints
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// Define if you want HW Breakpoints
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// (if HW breakpoints are not implemented
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// (if HW breakpoints are not implemented
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// only default software trapping is
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// only default software trapping is
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| Line 920... |
Line 920... |
`endif
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`endif
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`define OR1200_DU_DSR 11'd20
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`define OR1200_DU_DSR 11'd20
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`define OR1200_DU_DRR 11'd21
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`define OR1200_DU_DRR 11'd21
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`ifdef OR1200_DU_TB_IMPLEMENTED
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`ifdef OR1200_DU_TB_IMPLEMENTED
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`define OR1200_DU_TBADR 11'h0ff
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`define OR1200_DU_TBADR 11'h0ff
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`define OR1200_DU_TBIA 11'h1xx
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`define OR1200_DU_TBIA 11'h1??
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`define OR1200_DU_TBIM 11'h2xx
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`define OR1200_DU_TBIM 11'h2??
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`define OR1200_DU_TBAR 11'h3xx
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`define OR1200_DU_TBAR 11'h3??
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`define OR1200_DU_TBTS 11'h4xx
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`define OR1200_DU_TBTS 11'h4??
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`endif
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`endif
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// Position of offset bits inside SPR address
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// Position of offset bits inside SPR address
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`define OR1200_DUOFS_BITS 10:0
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`define OR1200_DUOFS_BITS 10:0
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| Line 1629... |
Line 1629... |
`define OR1200_DCCFGR_CBWBRI 1'b0 // Irrelevant
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`define OR1200_DCCFGR_CBWBRI 1'b0 // Irrelevant
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`define OR1200_DCCFGR_RES1 17'h00000
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`define OR1200_DCCFGR_RES1 17'h00000
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`else
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`else
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`define OR1200_DCCFGR_NCW 3'h0 // 1 cache way
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`define OR1200_DCCFGR_NCW 3'h0 // 1 cache way
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`define OR1200_DCCFGR_NCS (`OR1200_DCTAG) // Num cache sets
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`define OR1200_DCCFGR_NCS (`OR1200_DCTAG) // Num cache sets
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`define OR1200_DCCFGR_CBS (`OR1200_DCLS-4) // 16 byte cache block
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`define OR1200_DCCFGR_CBS `OR1200_DCLS==4 ? 1'b0 : 1'b1 // 16 byte cache block
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`ifdef OR1200_DC_WRITETHROUGH
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`ifdef OR1200_DC_WRITETHROUGH
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`define OR1200_DCCFGR_CWS 1'b0 // Write-through strategy
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`define OR1200_DCCFGR_CWS 1'b0 // Write-through strategy
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`else
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`else
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`define OR1200_DCCFGR_CWS 1'b1 // Write-back strategy
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`define OR1200_DCCFGR_CWS 1'b1 // Write-back strategy
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`endif
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`endif
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| Line 1677... |
Line 1677... |
`define OR1200_ICCFGR_CBWBRI 1'b0 // Irrelevant
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`define OR1200_ICCFGR_CBWBRI 1'b0 // Irrelevant
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`define OR1200_ICCFGR_RES1 17'h00000
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`define OR1200_ICCFGR_RES1 17'h00000
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`else
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`else
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`define OR1200_ICCFGR_NCW 3'h0 // 1 cache way
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`define OR1200_ICCFGR_NCW 3'h0 // 1 cache way
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`define OR1200_ICCFGR_NCS (`OR1200_ICTAG) // Num cache sets
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`define OR1200_ICCFGR_NCS (`OR1200_ICTAG) // Num cache sets
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`define OR1200_ICCFGR_CBS (`OR1200_ICLS-4) // 16 byte cache block
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`define OR1200_ICCFGR_CBS `OR1200_ICLS==4 ? 1'b0: 1'b1 // 16 byte cache block
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`define OR1200_ICCFGR_CWS 1'b0 // Irrelevant
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`define OR1200_ICCFGR_CWS 1'b0 // Irrelevant
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`define OR1200_ICCFGR_CCRI 1'b1 // Cache control reg impl.
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`define OR1200_ICCFGR_CCRI 1'b1 // Cache control reg impl.
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`define OR1200_ICCFGR_CBIRI 1'b1 // Cache block inv reg impl.
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`define OR1200_ICCFGR_CBIRI 1'b1 // Cache block inv reg impl.
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`define OR1200_ICCFGR_CBPRI 1'b0 // Cache block prefetch reg not impl.
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`define OR1200_ICCFGR_CBPRI 1'b0 // Cache block prefetch reg not impl.
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`define OR1200_ICCFGR_CBLRI 1'b0 // Cache block lock reg not impl.
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`define OR1200_ICCFGR_CBLRI 1'b0 // Cache block lock reg not impl.
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| Line 1705... |
Line 1705... |
`endif
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`endif
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`else
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`else
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`define OR1200_DCFGR_NDP 4'h0 // Zero DVR/DCR pairs
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`define OR1200_DCFGR_NDP 4'h0 // Zero DVR/DCR pairs
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`define OR1200_DCFGR_WPCI 1'b0 // WP counters not impl.
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`define OR1200_DCFGR_WPCI 1'b0 // WP counters not impl.
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`endif
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`endif
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`define OR1200_DCFGR_RES1 28'h0000000
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`define OR1200_DCFGR_RES1 27'd0
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///////////////////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////////////////
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// Boot Address Selection //
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// Boot Address Selection //
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// This only changes where the initial reset occurs. EPH setting is still //
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// This only changes where the initial reset occurs. EPH setting is still //
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// used to determine where vectors are located. //
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// used to determine where vectors are located. //
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