| Line 1656... |
Line 1656... |
`define OR1200_DMMUCFGR_NTW 2'h0 // 1 TLB way
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`define OR1200_DMMUCFGR_NTW 2'h0 // 1 TLB way
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`define OR1200_DMMUCFGR_NTS 3'h`OR1200_DTLB_INDXW // Num TLB sets
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`define OR1200_DMMUCFGR_NTS 3'h`OR1200_DTLB_INDXW // Num TLB sets
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`define OR1200_DMMUCFGR_NAE 3'h0 // No ATB entries
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`define OR1200_DMMUCFGR_NAE 3'h0 // No ATB entries
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`define OR1200_DMMUCFGR_CRI 1'b0 // No control register
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`define OR1200_DMMUCFGR_CRI 1'b0 // No control register
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`define OR1200_DMMUCFGR_PRI 1'b0 // No protection reg
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`define OR1200_DMMUCFGR_PRI 1'b0 // No protection reg
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`define OR1200_DMMUCFGR_TEIRI 1'b1 // TLB entry inv reg impl.
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`define OR1200_DMMUCFGR_TEIRI 1'b0 // TLB entry inv reg NOT impl.
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`define OR1200_DMMUCFGR_HTR 1'b0 // No HW TLB reload
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`define OR1200_DMMUCFGR_HTR 1'b0 // No HW TLB reload
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`define OR1200_DMMUCFGR_RES1 20'h00000
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`define OR1200_DMMUCFGR_RES1 20'h00000
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`endif
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`endif
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// IMMUCFGR fields
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// IMMUCFGR fields
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| Line 1687... |
Line 1687... |
`define OR1200_IMMUCFGR_NTW 2'h0 // 1 TLB way
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`define OR1200_IMMUCFGR_NTW 2'h0 // 1 TLB way
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`define OR1200_IMMUCFGR_NTS 3'h`OR1200_ITLB_INDXW // Num TLB sets
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`define OR1200_IMMUCFGR_NTS 3'h`OR1200_ITLB_INDXW // Num TLB sets
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`define OR1200_IMMUCFGR_NAE 3'h0 // No ATB entry
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`define OR1200_IMMUCFGR_NAE 3'h0 // No ATB entry
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`define OR1200_IMMUCFGR_CRI 1'b0 // No control reg
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`define OR1200_IMMUCFGR_CRI 1'b0 // No control reg
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`define OR1200_IMMUCFGR_PRI 1'b0 // No protection reg
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`define OR1200_IMMUCFGR_PRI 1'b0 // No protection reg
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`define OR1200_IMMUCFGR_TEIRI 1'b1 // TLB entry inv reg impl
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`define OR1200_IMMUCFGR_TEIRI 1'b0 // TLB entry inv reg NOT impl
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`define OR1200_IMMUCFGR_HTR 1'b0 // No HW TLB reload
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`define OR1200_IMMUCFGR_HTR 1'b0 // No HW TLB reload
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`define OR1200_IMMUCFGR_RES1 20'h00000
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`define OR1200_IMMUCFGR_RES1 20'h00000
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`endif
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`endif
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// DCCFGR fields
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// DCCFGR fields
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