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//////////////////////////////////////////////////////////////////////
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//// ////
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//// OR1200's ALU ////
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//// ////
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//// This file is part of the OpenRISC 1200 project ////
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//// http://www.opencores.org/project,or1k ////
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//// ////
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//// Description ////
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//// ALU ////
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//// ////
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//// To Do: ////
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//// - make it smaller and faster ////
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//// ////
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//// Author(s): ////
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//// - Damjan Lampret, lampret@opencores.org ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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// $Log: or1200_alu.v,v $
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// Revision 2.0 2010/06/30 11:00:00 ORSoC
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// Minor update:
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// Defines added, flags are corrected.
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// synopsys translate_off
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`include "timescale.v"
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// synopsys translate_on
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`include "or1200_defines.v"
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module or1200_alu(
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a, b, mult_mac_result, macrc_op,
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alu_op, shrot_op, comp_op,
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cust5_op, cust5_limm,
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result, flagforw, flag_we,
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cyforw, cy_we, carry, flag
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);
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parameter width = `OR1200_OPERAND_WIDTH;
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//
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// I/O
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//
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input [width-1:0] a;
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input [width-1:0] b;
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input [width-1:0] mult_mac_result;
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input macrc_op;
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input [`OR1200_ALUOP_WIDTH-1:0] alu_op;
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input [`OR1200_SHROTOP_WIDTH-1:0] shrot_op;
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input [`OR1200_COMPOP_WIDTH-1:0] comp_op;
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input [4:0] cust5_op;
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input [5:0] cust5_limm;
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output [width-1:0] result;
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output flagforw;
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output flag_we;
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output cyforw;
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output cy_we;
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input carry;
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input flag;
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//
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// Internal wires and regs
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//
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reg [width-1:0] result;
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reg [width-1:0] shifted_rotated;
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reg [width-1:0] result_cust5;
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reg flagforw;
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reg flagcomp;
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reg flag_we;
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reg cy_we;
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wire [width-1:0] comp_a;
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wire [width-1:0] comp_b;
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`ifdef OR1200_IMPL_ALU_COMP1
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wire a_eq_b;
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wire a_lt_b;
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`endif
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wire [width-1:0] result_sum;
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`ifdef OR1200_IMPL_ADDC
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wire [width-1:0] result_csum;
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wire cy_csum;
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`endif
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wire [width-1:0] result_and;
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wire cy_sum;
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`ifdef OR1200_IMPL_SUB
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wire cy_sub;
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`endif
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reg cyforw;
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//
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// Combinatorial logic
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//
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assign comp_a = {a[width-1] ^ comp_op[3] , a[width-2:0]};
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assign comp_b = {b[width-1] ^ comp_op[3] , b[width-2:0]};
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`ifdef OR1200_IMPL_ALU_COMP1
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assign a_eq_b = (comp_a == comp_b);
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assign a_lt_b = (comp_a < comp_b);
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`endif
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`ifdef OR1200_IMPL_SUB
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assign cy_sub = a < b;
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`endif
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assign {cy_sum, result_sum} = a + b;
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`ifdef OR1200_IMPL_ADDC
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assign {cy_csum, result_csum} = a + b + {`OR1200_OPERAND_WIDTH'd0, carry};
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`endif
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assign result_and = a & b;
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//
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// Simulation check for bad ALU behavior
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//
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`ifdef OR1200_WARNINGS
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// synopsys translate_off
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always @(result) begin
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if (result === 32'bx)
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$display("%t: WARNING: 32'bx detected on ALU result bus. Please check !", $time);
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end
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// synopsys translate_on
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`endif
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//
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// Central part of the ALU
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//
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always @(alu_op or a or b or result_sum or result_and or macrc_op or shifted_rotated or mult_mac_result or flag or result_cust5 or carry
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`ifdef OR1200_IMPL_ADDC
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or result_csum
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`endif
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) begin
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`ifdef OR1200_CASE_DEFAULT
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casex (alu_op) // synopsys parallel_case
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`else
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casex (alu_op) // synopsys full_case parallel_case
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`endif
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`OR1200_ALUOP_FF1: begin
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result = a[0] ? 1 : a[1] ? 2 : a[2] ? 3 : a[3] ? 4 : a[4] ? 5 : a[5] ? 6 : a[6] ? 7 : a[7] ? 8 : a[8] ? 9 : a[9] ? 10 : a[10] ? 11 : a[11] ? 12 : a[12] ? 13 : a[13] ? 14 : a[14] ? 15 : a[15] ? 16 : a[16] ? 17 : a[17] ? 18 : a[18] ? 19 : a[19] ? 20 : a[20] ? 21 : a[21] ? 22 : a[22] ? 23 : a[23] ? 24 : a[24] ? 25 : a[25] ? 26 : a[26] ? 27 : a[27] ? 28 : a[28] ? 29 : a[29] ? 30 : a[30] ? 31 : a[31] ? 32 : 0;
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end
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`OR1200_ALUOP_CUST5 : begin
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result = result_cust5;
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end
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`OR1200_ALUOP_SHROT : begin
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result = shifted_rotated;
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end
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`OR1200_ALUOP_ADD : begin
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result = result_sum;
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end
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`ifdef OR1200_IMPL_ADDC
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`OR1200_ALUOP_ADDC : begin
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result = result_csum;
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end
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`endif
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`ifdef OR1200_IMPL_SUB
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`OR1200_ALUOP_SUB : begin
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result = a - b;
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end
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`endif
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`OR1200_ALUOP_XOR : begin
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result = a ^ b;
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end
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`OR1200_ALUOP_OR : begin
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result = a | b;
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end
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`OR1200_ALUOP_IMM : begin
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result = b;
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end
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`OR1200_ALUOP_MOVHI : begin
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if (macrc_op) begin
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result = mult_mac_result;
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end
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else begin
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result = b << 16;
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end
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end
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`ifdef OR1200_MULT_IMPLEMENTED
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`ifdef OR1200_DIV_IMPLEMENTED
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`OR1200_ALUOP_DIV,
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`OR1200_ALUOP_DIVU,
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`endif
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`OR1200_ALUOP_MUL : begin
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result = mult_mac_result;
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end
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`endif
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`OR1200_ALUOP_CMOV: begin
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result = flag ? a : b;
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end
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`ifdef OR1200_CASE_DEFAULT
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default: begin
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`else
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`OR1200_ALUOP_COMP, `OR1200_ALUOP_AND: begin
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`endif
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result=result_and;
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end
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endcase
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end
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//
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// l.cust5 custom instructions
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//
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// Examples for move byte, set bit and clear bit
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//
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always @(cust5_op or cust5_limm or a or b) begin
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casex (cust5_op) // synopsys parallel_case
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5'h1 : begin
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casex (cust5_limm[1:0])
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2'h0: result_cust5 = {a[31:8], b[7:0]};
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2'h1: result_cust5 = {a[31:16], b[7:0], a[7:0]};
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2'h2: result_cust5 = {a[31:24], b[7:0], a[15:0]};
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2'h3: result_cust5 = {b[7:0], a[23:0]};
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endcase
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end
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5'h2 :
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result_cust5 = a | (1 << cust5_limm);
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5'h3 :
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result_cust5 = a & (32'hffffffff ^ (1 << cust5_limm));
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//
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// *** Put here new l.cust5 custom instructions ***
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//
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default: begin
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result_cust5 = a;
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end
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endcase
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end
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//
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// Generate flag and flag write enable
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//
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always @(alu_op or result_sum or result_and or flagcomp
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`ifdef OR1200_IMPL_ADDC
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or result_csum
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`endif
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) begin
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casex (alu_op) // synopsys parallel_case
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`ifdef OR1200_ADDITIONAL_FLAG_MODIFIERS
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`OR1200_ALUOP_ADD : begin
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flagforw = (result_sum == 32'h0000_0000);
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flag_we = 1'b1;
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end
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`ifdef OR1200_IMPL_ADDC
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`OR1200_ALUOP_ADDC : begin
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flagforw = (result_csum == 32'h0000_0000);
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flag_we = 1'b1;
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end
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`endif
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`OR1200_ALUOP_AND: begin
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flagforw = (result_and == 32'h0000_0000);
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flag_we = 1'b1;
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end
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`endif
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`OR1200_ALUOP_COMP: begin
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flagforw = flagcomp;
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flag_we = 1'b1;
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end
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default: begin
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flagforw = flagcomp;
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flag_we = 1'b0;
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end
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endcase
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end
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//
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// Generate SR[CY] write enable
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//
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always @(alu_op or cy_sum
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`ifdef OR1200_IMPL_CY
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`ifdef OR1200_IMPL_ADDC
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or cy_csum
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`endif
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`ifdef OR1200_IMPL_SUB
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or cy_sub
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`endif
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`endif
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) begin
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casex (alu_op) // synopsys parallel_case
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`ifdef OR1200_IMPL_CY
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`OR1200_ALUOP_ADD : begin
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cyforw = cy_sum;
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cy_we = 1'b1;
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end
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`ifdef OR1200_IMPL_ADDC
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`OR1200_ALUOP_ADDC: begin
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cyforw = cy_csum;
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cy_we = 1'b1;
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end
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`endif
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`ifdef OR1200_IMPL_SUB
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`OR1200_ALUOP_SUB: begin
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cyforw = cy_sub;
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cy_we = 1'b1;
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end
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`endif
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`endif
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default: begin
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cyforw = 1'b0;
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cy_we = 1'b0;
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end
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endcase
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end
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//
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// Shifts and rotation
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//
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always @(shrot_op or a or b) begin
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case (shrot_op) // synopsys parallel_case
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`OR1200_SHROTOP_SLL :
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shifted_rotated = (a << b[4:0]);
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`OR1200_SHROTOP_SRL :
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shifted_rotated = (a >> b[4:0]);
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`ifdef OR1200_IMPL_ALU_ROTATE
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`OR1200_SHROTOP_ROR :
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shifted_rotated = (a << (6'd32-{1'b0, b[4:0]})) | (a >> b[4:0]);
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`endif
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default:
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shifted_rotated = ({32{a[31]}} << (6'd32-{1'b0, b[4:0]})) | a >> b[4:0];
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endcase
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end
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//
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// First type of compare implementation
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//
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`ifdef OR1200_IMPL_ALU_COMP1
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always @(comp_op or a_eq_b or a_lt_b) begin
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case(comp_op[2:0]) // synopsys parallel_case
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`OR1200_COP_SFEQ:
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flagcomp = a_eq_b;
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`OR1200_COP_SFNE:
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flagcomp = ~a_eq_b;
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`OR1200_COP_SFGT:
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flagcomp = ~(a_eq_b | a_lt_b);
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`OR1200_COP_SFGE:
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flagcomp = ~a_lt_b;
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`OR1200_COP_SFLT:
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flagcomp = a_lt_b;
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`OR1200_COP_SFLE:
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flagcomp = a_eq_b | a_lt_b;
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default:
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flagcomp = 1'b0;
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endcase
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end
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`endif
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//
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// Second type of compare implementation
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//
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`ifdef OR1200_IMPL_ALU_COMP2
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always @(comp_op or comp_a or comp_b) begin
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case(comp_op[2:0]) // synopsys parallel_case
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`OR1200_COP_SFEQ:
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flagcomp = (comp_a == comp_b);
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`OR1200_COP_SFNE:
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flagcomp = (comp_a != comp_b);
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`OR1200_COP_SFGT:
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flagcomp = (comp_a > comp_b);
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`OR1200_COP_SFGE:
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flagcomp = (comp_a >= comp_b);
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`OR1200_COP_SFLT:
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flagcomp = (comp_a < comp_b);
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`OR1200_COP_SFLE:
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flagcomp = (comp_a <= comp_b);
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default:
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flagcomp = 1'b0;
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endcase
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end
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`endif
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endmodule
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