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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [or1200/] [or1200_alu.v] - Diff between revs 435 and 499

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Line 51... Line 51...
// synopsys translate_on
// synopsys translate_on
`include "or1200_defines.v"
`include "or1200_defines.v"
 
 
module or1200_alu(
module or1200_alu(
        a, b, mult_mac_result, macrc_op,
        a, b, mult_mac_result, macrc_op,
        alu_op, alu_op2, shrot_op, comp_op,
        alu_op, alu_op2, comp_op,
        cust5_op, cust5_limm,
        cust5_op, cust5_limm,
        result, flagforw, flag_we,
        result, flagforw, flag_we,
        cyforw, cy_we, carry, flag
        cyforw, cy_we, carry, flag
);
);
 
 
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input   [width-1:0]              b;
input   [width-1:0]              b;
input   [width-1:0]              mult_mac_result;
input   [width-1:0]              mult_mac_result;
input                           macrc_op;
input                           macrc_op;
input   [`OR1200_ALUOP_WIDTH-1:0]        alu_op;
input   [`OR1200_ALUOP_WIDTH-1:0]        alu_op;
input   [`OR1200_ALUOP2_WIDTH-1:0]       alu_op2;
input   [`OR1200_ALUOP2_WIDTH-1:0]       alu_op2;
input   [`OR1200_SHROTOP_WIDTH-1:0]      shrot_op;
 
input   [`OR1200_COMPOP_WIDTH-1:0]       comp_op;
input   [`OR1200_COMPOP_WIDTH-1:0]       comp_op;
input   [4:0]                    cust5_op;
input   [4:0]                    cust5_op;
input   [5:0]                    cust5_limm;
input   [5:0]                    cust5_limm;
output  [width-1:0]              result;
output  [width-1:0]              result;
output                          flagforw;
output                          flagforw;
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//
//
// Internal wires and regs
// Internal wires and regs
//
//
reg     [width-1:0]              result;
reg     [width-1:0]              result;
reg     [width-1:0]              shifted_rotated;
reg     [width-1:0]              shifted_rotated;
 
reg     [width-1:0]              extended;
reg     [width-1:0]              result_cust5;
reg     [width-1:0]              result_cust5;
reg                             flagforw;
reg                             flagforw;
reg                             flagcomp;
reg                             flagcomp;
reg                             flag_we;
reg                             flag_we;
reg                             cy_we;
reg                             cy_we;
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always @(alu_op or alu_op2 or a or b or result_sum or result_and or macrc_op
always @(alu_op or alu_op2 or a or b or result_sum or result_and or macrc_op
         or shifted_rotated or mult_mac_result or flag or result_cust5 or carry
         or shifted_rotated or mult_mac_result or flag or result_cust5 or carry
`ifdef OR1200_IMPL_ADDC
`ifdef OR1200_IMPL_ADDC
         or result_csum
         or result_csum
`endif
`endif
 
`ifdef OR1200_IMPL_ALU_EXT
 
         or extended
 
`endif
) begin
) begin
`ifdef OR1200_CASE_DEFAULT
`ifdef OR1200_CASE_DEFAULT
        casez (alu_op)          // synopsys parallel_case
        casez (alu_op)          // synopsys parallel_case
`else
`else
        casez (alu_op)          // synopsys full_case parallel_case
        casez (alu_op)          // synopsys full_case parallel_case
Line 167... Line 170...
                     default: begin // FL1
                     default: begin // FL1
                        result = a[31] ? 32 : a[30] ? 31 : a[29] ? 30 : a[28] ? 29 : a[27] ? 28 : a[26] ? 27 : a[25] ? 26 : a[24] ? 25 : a[23] ? 24 : a[22] ? 23 : a[21] ? 22 : a[20] ? 21 : a[19] ? 20 : a[18] ? 19 : a[17] ? 18 : a[16] ? 17 : a[15] ? 16 : a[14] ? 15 : a[13] ? 14 : a[12] ? 13 : a[11] ? 12 : a[10] ? 11 : a[9] ? 10 : a[8] ? 9 : a[7] ? 8 : a[6] ? 7 : a[5] ? 6 : a[4] ? 5 : a[3] ? 4 : a[2] ? 3 : a[1] ? 2 : a[0] ? 1 : 0 ;
                        result = a[31] ? 32 : a[30] ? 31 : a[29] ? 30 : a[28] ? 29 : a[27] ? 28 : a[26] ? 27 : a[25] ? 26 : a[24] ? 25 : a[23] ? 24 : a[22] ? 23 : a[21] ? 22 : a[20] ? 21 : a[19] ? 20 : a[18] ? 19 : a[17] ? 18 : a[16] ? 17 : a[15] ? 16 : a[14] ? 15 : a[13] ? 14 : a[12] ? 13 : a[11] ? 12 : a[10] ? 11 : a[9] ? 10 : a[8] ? 9 : a[7] ? 8 : a[6] ? 7 : a[5] ? 6 : a[4] ? 5 : a[3] ? 4 : a[2] ? 3 : a[1] ? 2 : a[0] ? 1 : 0 ;
                     end
                     end
                   endcase // casez (alu_op2)
                   endcase // casez (alu_op2)
                end // case: `OR1200_ALUOP_FFL1
                end // case: `OR1200_ALUOP_FFL1
`endif
`endif //  `ifdef OR1200_IMPL_ALU_FFL1
 
`ifdef OR1200_IMPL_ALU_CUST5
 
 
                `OR1200_ALUOP_CUST5 : begin
                `OR1200_ALUOP_CUST5 : begin
                                result = result_cust5;
                                result = result_cust5;
                end
                end
 
`endif
                `OR1200_ALUOP_SHROT : begin
                `OR1200_ALUOP_SHROT : begin
                                result = shifted_rotated;
                                result = shifted_rotated;
                end
                end
                `OR1200_ALUOP_ADD : begin
                `OR1200_ALUOP_ADD : begin
                                result = result_sum;
                                result = result_sum;
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                                result = a ^ b;
                                result = a ^ b;
                end
                end
                `OR1200_ALUOP_OR  : begin
                `OR1200_ALUOP_OR  : begin
                                result = a | b;
                                result = a | b;
                end
                end
 
`ifdef OR1200_IMPL_ALU_EXT
 
                `OR1200_ALUOP_EXTHB  : begin
 
                                result = extended;
 
                end
 
                `OR1200_ALUOP_EXTW  : begin
 
                                result = extended;
 
                end
 
`endif
                `OR1200_ALUOP_MOVHI : begin
                `OR1200_ALUOP_MOVHI : begin
                                if (macrc_op) begin
                                if (macrc_op) begin
                                        result = mult_mac_result;
                                        result = mult_mac_result;
                                end
                                end
                                else begin
                                else begin
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                end
                end
        endcase
        endcase
end
end
 
 
//
//
// l.cust5 custom instructions
 
//
 
// Examples for move byte, set bit and clear bit
 
//
 
always @(cust5_op or cust5_limm or a or b) begin
 
        casez (cust5_op)                // synopsys parallel_case
 
                5'h1 : begin
 
                        casez (cust5_limm[1:0])
 
                                2'h0: result_cust5 = {a[31:8], b[7:0]};
 
                                2'h1: result_cust5 = {a[31:16], b[7:0], a[7:0]};
 
                                2'h2: result_cust5 = {a[31:24], b[7:0], a[15:0]};
 
                                2'h3: result_cust5 = {b[7:0], a[23:0]};
 
                        endcase
 
                end
 
                5'h2 :
 
                        result_cust5 = a | (1 << cust5_limm);
 
                5'h3 :
 
                        result_cust5 = a & (32'hffffffff ^ (1 << cust5_limm));
 
//
 
// *** Put here new l.cust5 custom instructions ***
 
//
 
                default: begin
 
                        result_cust5 = a;
 
                end
 
        endcase
 
end
 
 
 
//
 
// Generate flag and flag write enable
// Generate flag and flag write enable
//
//
always @(alu_op or result_sum or result_and or flagcomp
always @(alu_op or result_sum or result_and or flagcomp
`ifdef OR1200_IMPL_ADDC
`ifdef OR1200_IMPL_ADDC
         or result_csum
         or result_csum
Line 331... Line 317...
end
end
 
 
//
//
// Shifts and rotation
// Shifts and rotation
//
//
always @(shrot_op or a or b) begin
always @(alu_op2 or a or b) begin
        case (shrot_op)         // synopsys parallel_case
        case (alu_op2)          // synopsys parallel_case
        `OR1200_SHROTOP_SLL :
        `OR1200_SHROTOP_SLL :
                                shifted_rotated = (a << b[4:0]);
                                shifted_rotated = (a << b[4:0]);
                `OR1200_SHROTOP_SRL :
                `OR1200_SHROTOP_SRL :
                                shifted_rotated = (a >> b[4:0]);
                                shifted_rotated = (a >> b[4:0]);
 
 
`ifdef OR1200_IMPL_ALU_ROTATE
`ifdef OR1200_IMPL_ALU_ROTATE
                `OR1200_SHROTOP_ROR :
                `OR1200_SHROTOP_ROR :
                                shifted_rotated = (a << (6'd32-{1'b0, b[4:0]})) | (a >> b[4:0]);
                                shifted_rotated = (a << (6'd32-{1'b0,b[4:0]})) |
 
                                                  (a >> b[4:0]);
`endif
`endif
                default:
                default:
                                shifted_rotated = ({32{a[31]}} << (6'd32-{1'b0, b[4:0]})) | a >> b[4:0];
                                shifted_rotated = ({32{a[31]}} <<
 
                                                   (6'd32-{1'b0, b[4:0]})) |
 
                                                  a >> b[4:0];
        endcase
        endcase
end
end
 
 
//
//
// First type of compare implementation
// First type of compare implementation
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                        flagcomp = 1'b0;
                        flagcomp = 1'b0;
        endcase
        endcase
end
end
`endif
`endif
 
 
 
`ifdef OR1200_IMPL_ALU_EXT
 
   always @(alu_op or alu_op2 or a) begin
 
      casez (alu_op2)
 
        `OR1200_EXTHBOP_HS : extended = {{16{a[15]}},a[15:0]};
 
        `OR1200_EXTHBOP_BS : extended = {{24{a[7]}},a[7:0]};
 
        `OR1200_EXTHBOP_HZ : extended = {16'd0,a[15:0]};
 
        `OR1200_EXTHBOP_BZ : extended = {24'd0,a[7:0]};
 
        default: extended = a; // Used for l.extw instructions
 
      endcase // casez (alu_op2)
 
   end
 
`endif
 
 
 
 
 
//
 
// l.cust5 custom instructions
 
//
 
`ifdef OR1200_IMPL_ALU_CUST5
 
// Examples for move byte, set bit and clear bit
 
//
 
always @(cust5_op or cust5_limm or a or b) begin
 
        casez (cust5_op)                // synopsys parallel_case
 
                5'h1 : begin
 
                        casez (cust5_limm[1:0])
 
                          2'h0: result_cust5 = {a[31:8], b[7:0]};
 
                          2'h1: result_cust5 = {a[31:16], b[7:0], a[7:0]};
 
                          2'h2: result_cust5 = {a[31:24], b[7:0], a[15:0]};
 
                          2'h3: result_cust5 = {b[7:0], a[23:0]};
 
                        endcase
 
                end
 
                5'h2 :
 
                        result_cust5 = a | (1 << cust5_limm);
 
                5'h3 :
 
                        result_cust5 = a & (32'hffffffff ^ (1 << cust5_limm));
 
//
 
// *** Put here new l.cust5 custom instructions ***
 
//
 
                default: begin
 
                        result_cust5 = a;
 
                end
 
        endcase
 
end // always @ (cust5_op or cust5_limm or a or b)
 
`endif
 
 
endmodule
endmodule
 
 
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