| Line 98... |
Line 98... |
reg cy_we;
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reg cy_we;
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reg ovforw;
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reg ovforw;
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reg ov_we;
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reg ov_we;
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wire [width-1:0] comp_a;
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wire [width-1:0] comp_a;
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wire [width-1:0] comp_b;
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wire [width-1:0] comp_b;
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`ifdef OR1200_IMPL_ALU_COMP1
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wire a_eq_b;
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wire a_eq_b;
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wire a_lt_b;
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wire a_lt_b;
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`endif
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wire [width-1:0] result_sum;
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wire [width-1:0] result_sum;
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wire [width-1:0] result_and;
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wire [width-1:0] result_and;
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wire cy_sum;
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wire cy_sum;
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`ifdef OR1200_IMPL_SUB
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`ifdef OR1200_IMPL_SUB
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wire cy_sub;
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wire cy_sub;
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| Line 118... |
Line 116... |
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//
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//
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// Combinatorial logic
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// Combinatorial logic
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//
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//
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assign comp_a = {a[width-1] ^ comp_op[3] , a[width-2:0]};
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assign comp_a = {a[width-1] ^ comp_op[3] , a[width-2:0]};
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assign comp_b = {b[width-1] ^ comp_op[3] , b[width-2:0]};
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assign comp_b = {b[width-1] ^ comp_op[3] , b[width-2:0]};
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`ifdef OR1200_IMPL_ALU_COMP1
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`ifdef OR1200_IMPL_ALU_COMP1
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assign a_eq_b = (comp_a == comp_b);
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assign a_eq_b = (comp_a == comp_b);
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assign a_lt_b = (comp_a < comp_b);
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assign a_lt_b = (comp_a < comp_b);
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`endif
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`endif
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`ifdef OR1200_IMPL_ALU_COMP3
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assign a_eq_b = !(|result_sum);
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assign a_lt_b = comp_op[3] ? ((a[width-1] & !b[width-1]) |
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(!a[width-1] & !b[width-1] & result_sum[width-1])|
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(a[width-1] & b[width-1] & result_sum[width-1])):
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result_sum[width-1];
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`endif
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`ifdef OR1200_IMPL_SUB
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`ifdef OR1200_IMPL_SUB
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`ifdef OR1200_IMPL_ALU_COMP3
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assign cy_sub = a_lt_b;
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`else
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assign cy_sub = (comp_a < comp_b);
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assign cy_sub = (comp_a < comp_b);
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`endif
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`endif
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`endif
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`ifdef OR1200_IMPL_ADDC
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`ifdef OR1200_IMPL_ADDC
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assign carry_in = (alu_op==`OR1200_ALUOP_ADDC) ?
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assign carry_in = (alu_op==`OR1200_ALUOP_ADDC) ?
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{{width-1{1'b0}},carry} : {width{1'b0}};
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{{width-1{1'b0}},carry} : {width{1'b0}};
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`else
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`else
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assign carry_in = {width-1{1'b0}};
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assign carry_in = {width-1{1'b0}};
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`endif
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`endif
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`ifdef OR1200_IMPL_ALU_COMP3
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`ifdef OR1200_IMPL_SUB
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assign b_mux = ((alu_op==`OR1200_ALUOP_SUB) | (alu_op==`OR1200_ALUOP_COMP)) ?
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(~b)+1 : b;
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`else
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assign b_mux = (alu_op==`OR1200_ALUOP_COMP) ? (~b)+1 : b;
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`endif
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`else // ! `ifdef OR1200_IMPL_ALU_COMP3
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`ifdef OR1200_IMPL_SUB
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`ifdef OR1200_IMPL_SUB
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assign b_mux = (alu_op==`OR1200_ALUOP_SUB) ? (~b)+1 : b;
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assign b_mux = (alu_op==`OR1200_ALUOP_SUB) ? (~b)+1 : b;
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`else
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`else
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assign b_mux = b;
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assign b_mux = b;
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`endif
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`endif
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`endif
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assign {cy_sum, result_sum} = (a + b_mux) + carry_in;
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assign {cy_sum, result_sum} = (a + b_mux) + carry_in;
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// Numbers either both +ve and bit 31 of result set
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// Numbers either both +ve and bit 31 of result set
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assign ov_sum = ((!a[width-1] & !b_mux[width-1]) & result_sum[width-1]) |
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assign ov_sum = ((!a[width-1] & !b_mux[width-1]) & result_sum[width-1]) |
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// or both -ve and bit 31 of result clear
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// or both -ve and bit 31 of result clear
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((a[width-1] & b_mux[width-1]) & !result_sum[width-1]);
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((a[width-1] & b_mux[width-1]) & !result_sum[width-1]);
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| Line 407... |
Line 429... |
flagcomp = (comp_a <= comp_b);
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flagcomp = (comp_a <= comp_b);
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default:
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default:
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flagcomp = 1'b0;
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flagcomp = 1'b0;
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endcase
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endcase
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end
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end
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`endif // `ifdef OR1200_IMPL_ALU_COMP2
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`ifdef OR1200_IMPL_ALU_COMP3
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always @(comp_op or a_eq_b or a_lt_b) begin
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case(comp_op[2:0]) // synopsys parallel_case
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`OR1200_COP_SFEQ:
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flagcomp = a_eq_b;
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`OR1200_COP_SFNE:
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flagcomp = ~a_eq_b;
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`OR1200_COP_SFGT:
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flagcomp = ~(a_eq_b | a_lt_b);
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`OR1200_COP_SFGE:
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flagcomp = ~a_lt_b;
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`OR1200_COP_SFLT:
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flagcomp = a_lt_b;
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`OR1200_COP_SFLE:
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flagcomp = a_eq_b | a_lt_b;
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default:
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flagcomp = 1'b0;
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endcase
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end
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`endif
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`endif
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`ifdef OR1200_IMPL_ALU_EXT
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`ifdef OR1200_IMPL_ALU_EXT
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always @(alu_op or alu_op2 or a) begin
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always @(alu_op or alu_op2 or a) begin
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casez (alu_op2)
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casez (alu_op2)
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`OR1200_EXTHBOP_HS : extended = {{16{a[15]}},a[15:0]};
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`OR1200_EXTHBOP_HS : extended = {{16{a[15]}},a[15:0]};
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`OR1200_EXTHBOP_BS : extended = {{24{a[7]}},a[7:0]};
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`OR1200_EXTHBOP_BS : extended = {{24{a[7]}},a[7:0]};
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