OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [or1200/] [or1200_alu.v] - Diff between revs 619 and 672

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 619 Rev 672
Line 129... Line 129... 
assign a_eq_b = !(|result_sum);
 
assign a_eq_b = !(|result_sum);
 
// signed compare when comp_op[3] is set
 
// signed compare when comp_op[3] is set
 
assign a_lt_b = comp_op[3] ? ((a[width-1] & !b[width-1]) |
 
assign a_lt_b = comp_op[3] ? ((a[width-1] & !b[width-1]) |
 
                              (!a[width-1] & !b[width-1] & result_sum[width-1])|
 
                              (!a[width-1] & !b[width-1] & result_sum[width-1])|
 
                              (a[width-1] & b[width-1] & result_sum[width-1])):
 
                              (a[width-1] & b[width-1] & result_sum[width-1])):
 
// a < b if (a - b) subtraction wrapped and a[width-1] wasn't set
 
                (a < b);
 
                (result_sum[width-1] & !a[width-1]) |
 
 
 
// or if (a - b) wrapped and both a[width-1] and b[width-1] were set
 
 
 
                (result_sum[width-1] & a[width-1] & b[width-1] );
 
 
 
`endif
 
`endif
 
 
 
 
 
`ifdef OR1200_IMPL_SUB
 
`ifdef OR1200_IMPL_SUB
 
 `ifdef OR1200_IMPL_ALU_COMP3
 
 `ifdef OR1200_IMPL_ALU_COMP3
 
assign cy_sub = a_lt_b;
 
assign cy_sub = a_lt_b;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.