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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [or1200/] [or1200_alu.v] - Diff between revs 672 and 788

Rev 672	Rev 788
Line 88...	Line 88...
`// Internal wires and regs`	`// Internal wires and regs`
`//`	`//`
`reg [width-1:0] result;`	`reg [width-1:0] result;`
`reg [width-1:0] shifted_rotated;`	`reg [width-1:0] shifted_rotated;`
`reg [width-1:0] extended;`	`reg [width-1:0] extended;`
	`ifdef OR1200_IMPL_ALU_CUST5
`reg [width-1:0] result_cust5;`	`reg [width-1:0] result_cust5;`
	`endif
`reg flagforw;`	`reg flagforw;`
`reg flagcomp;`	`reg flagcomp;`
`reg flag_we;`	`reg flag_we;`
`reg cyforw;`	`reg cyforw;`
`reg cy_we;`	`reg cy_we;`
Line 185...	Line 187...

`//`	`//`
`// Central part of the ALU`	`// Central part of the ALU`
`//`	`//`
`always @(alu_op or alu_op2 or a or b or result_sum or result_and or macrc_op`	`always @(alu_op or alu_op2 or a or b or result_sum or result_and or macrc_op`
`or shifted_rotated or mult_mac_result or flag or result_cust5 or carry`	`or shifted_rotated or mult_mac_result or flag or carry`
`ifdef OR1200_IMPL_ALU_EXT	`ifdef OR1200_IMPL_ALU_EXT
`or extended`	`or extended`
`endif	`endif
	`ifdef OR1200_IMPL_ALU_CUST5
	`or result_cust5`
	`endif
`) begin`	`) begin`
`ifdef OR1200_CASE_DEFAULT	`ifdef OR1200_CASE_DEFAULT
`casez (alu_op) // synopsys parallel_case`	`casez (alu_op) // synopsys parallel_case`
`else	`else
`casez (alu_op) // synopsys full_case parallel_case`	`casez (alu_op) // synopsys full_case parallel_case`