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module or1200_alu(
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module or1200_alu(
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a, b, mult_mac_result, macrc_op,
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a, b, mult_mac_result, macrc_op,
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alu_op, alu_op2, comp_op,
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alu_op, alu_op2, comp_op,
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cust5_op, cust5_limm,
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cust5_op, cust5_limm,
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result, flagforw, flag_we,
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result, flagforw, flag_we,
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ovforw, ov_we,
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cyforw, cy_we, carry, flag
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cyforw, cy_we, carry, flag
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);
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);
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parameter width = `OR1200_OPERAND_WIDTH;
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parameter width = `OR1200_OPERAND_WIDTH;
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Line 77... |
output [width-1:0] result;
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output [width-1:0] result;
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output flagforw;
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output flagforw;
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output flag_we;
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output flag_we;
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output cyforw;
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output cyforw;
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output cy_we;
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output cy_we;
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output ovforw;
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output ov_we;
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input carry;
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input carry;
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input flag;
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input flag;
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//
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//
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// Internal wires and regs
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// Internal wires and regs
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reg [width-1:0] extended;
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reg [width-1:0] extended;
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reg [width-1:0] result_cust5;
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reg [width-1:0] result_cust5;
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reg flagforw;
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reg flagforw;
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reg flagcomp;
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reg flagcomp;
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reg flag_we;
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reg flag_we;
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reg cyforw;
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reg cy_we;
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reg cy_we;
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reg ovforw;
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reg ov_we;
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wire [width-1:0] comp_a;
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wire [width-1:0] comp_a;
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wire [width-1:0] comp_b;
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wire [width-1:0] comp_b;
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`ifdef OR1200_IMPL_ALU_COMP1
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`ifdef OR1200_IMPL_ALU_COMP1
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wire a_eq_b;
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wire a_eq_b;
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wire a_lt_b;
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wire a_lt_b;
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`endif
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`endif
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wire [width-1:0] result_sum;
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wire [width-1:0] result_sum;
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`ifdef OR1200_IMPL_ADDC
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wire [width-1:0] result_csum;
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wire cy_csum;
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`endif
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wire [width-1:0] result_and;
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wire [width-1:0] result_and;
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wire cy_sum;
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wire cy_sum;
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`ifdef OR1200_IMPL_SUB
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`ifdef OR1200_IMPL_SUB
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wire cy_sub;
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wire cy_sub;
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`endif
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`endif
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reg cyforw;
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wire ov_sum;
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wire [width-1:0] carry_in;
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wire [width-1:0] b_mux;
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//
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//
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// Combinatorial logic
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// Combinatorial logic
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//
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//
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assign comp_a = {a[width-1] ^ comp_op[3] , a[width-2:0]};
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assign comp_a = {a[width-1] ^ comp_op[3] , a[width-2:0]};
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`ifdef OR1200_IMPL_ALU_COMP1
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`ifdef OR1200_IMPL_ALU_COMP1
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assign a_eq_b = (comp_a == comp_b);
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assign a_eq_b = (comp_a == comp_b);
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assign a_lt_b = (comp_a < comp_b);
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assign a_lt_b = (comp_a < comp_b);
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`endif
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`endif
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`ifdef OR1200_IMPL_SUB
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`ifdef OR1200_IMPL_SUB
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assign cy_sub = a < b;
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assign cy_sub = (comp_a < comp_b);
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`endif
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`endif
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assign {cy_sum, result_sum} = a + b;
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`ifdef OR1200_IMPL_ADDC
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`ifdef OR1200_IMPL_ADDC
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assign {cy_csum, result_csum} = a + b + {`OR1200_OPERAND_WIDTH'd0, carry};
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assign carry_in = (alu_op==`OR1200_ALUOP_ADDC) ?
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{{width-1{1'b0}},carry} : {width{1'b0}};
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`else
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assign carry_in = {width-1{1'b0}};
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`endif
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`ifdef OR1200_IMPL_SUB
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assign b_mux = (alu_op==`OR1200_ALUOP_SUB) ? (~b)+1 : b;
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`else
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assign b_mux = b;
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`endif
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`endif
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assign {cy_sum, result_sum} = (a + b_mux) + carry_in;
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// Numbers either both +ve and bit 31 of result set
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assign ov_sum = ((!a[width-1] & !b_mux[width-1]) & result_sum[width-1]) |
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// or both -ve and bit 31 of result clear
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((a[width-1] & b_mux[width-1]) & !result_sum[width-1]);
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assign result_and = a & b;
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assign result_and = a & b;
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//
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//
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// Simulation check for bad ALU behavior
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// Simulation check for bad ALU behavior
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//
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//
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//
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//
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// Central part of the ALU
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// Central part of the ALU
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//
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//
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always @(alu_op or alu_op2 or a or b or result_sum or result_and or macrc_op
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always @(alu_op or alu_op2 or a or b or result_sum or result_and or macrc_op
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or shifted_rotated or mult_mac_result or flag or result_cust5 or carry
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or shifted_rotated or mult_mac_result or flag or result_cust5 or carry
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`ifdef OR1200_IMPL_ADDC
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or result_csum
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`endif
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`ifdef OR1200_IMPL_ALU_EXT
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`ifdef OR1200_IMPL_ALU_EXT
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or extended
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or extended
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`endif
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`endif
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) begin
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) begin
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`ifdef OR1200_CASE_DEFAULT
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`ifdef OR1200_CASE_DEFAULT
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Line 196... |
end
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end
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`endif
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`endif
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`OR1200_ALUOP_SHROT : begin
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`OR1200_ALUOP_SHROT : begin
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result = shifted_rotated;
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result = shifted_rotated;
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end
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end
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`OR1200_ALUOP_ADD : begin
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result = result_sum;
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end
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`ifdef OR1200_IMPL_ADDC
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`ifdef OR1200_IMPL_ADDC
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`OR1200_ALUOP_ADDC : begin
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`OR1200_ALUOP_ADDC,
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result = result_csum;
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end
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`endif
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`endif
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`ifdef OR1200_IMPL_SUB
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`ifdef OR1200_IMPL_SUB
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`OR1200_ALUOP_SUB : begin
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`OR1200_ALUOP_SUB,
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result = a - b;
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end
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`endif
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`endif
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`OR1200_ALUOP_ADD : begin
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result = result_sum;
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end
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`OR1200_ALUOP_XOR : begin
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`OR1200_ALUOP_XOR : begin
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result = a ^ b;
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result = a ^ b;
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end
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end
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`OR1200_ALUOP_OR : begin
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`OR1200_ALUOP_OR : begin
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result = a | b;
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result = a | b;
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Line 255... |
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//
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//
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// Generate flag and flag write enable
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// Generate flag and flag write enable
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//
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//
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always @(alu_op or result_sum or result_and or flagcomp
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always @(alu_op or result_sum or result_and or flagcomp
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`ifdef OR1200_IMPL_ADDC
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or result_csum
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`endif
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) begin
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) begin
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casez (alu_op) // synopsys parallel_case
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casez (alu_op) // synopsys parallel_case
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`ifdef OR1200_ADDITIONAL_FLAG_MODIFIERS
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`ifdef OR1200_ADDITIONAL_FLAG_MODIFIERS
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`ifdef OR1200_IMPL_ADDC
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`OR1200_ALUOP_ADDC,
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`endif
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`OR1200_ALUOP_ADD : begin
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`OR1200_ALUOP_ADD : begin
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flagforw = (result_sum == 32'h0000_0000);
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flagforw = (result_sum == 32'h0000_0000);
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flag_we = 1'b1;
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flag_we = 1'b1;
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end
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end
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`ifdef OR1200_IMPL_ADDC
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`OR1200_ALUOP_ADDC : begin
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flagforw = (result_csum == 32'h0000_0000);
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flag_we = 1'b1;
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end
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`endif
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`OR1200_ALUOP_AND: begin
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`OR1200_ALUOP_AND: begin
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flagforw = (result_and == 32'h0000_0000);
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flagforw = (result_and == 32'h0000_0000);
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flag_we = 1'b1;
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flag_we = 1'b1;
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end
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end
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`endif
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`endif
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Line 286... |
//
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//
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// Generate SR[CY] write enable
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// Generate SR[CY] write enable
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//
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//
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always @(alu_op or cy_sum
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always @(alu_op or cy_sum
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`ifdef OR1200_IMPL_CY
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`ifdef OR1200_IMPL_CY
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`ifdef OR1200_IMPL_ADDC
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or cy_csum
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`endif
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`ifdef OR1200_IMPL_SUB
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`ifdef OR1200_IMPL_SUB
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or cy_sub
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or cy_sub
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`endif
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`endif
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`endif
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`endif
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) begin
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) begin
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casez (alu_op) // synopsys parallel_case
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casez (alu_op) // synopsys parallel_case
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`ifdef OR1200_IMPL_CY
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`ifdef OR1200_IMPL_CY
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`ifdef OR1200_IMPL_ADDC
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`OR1200_ALUOP_ADDC,
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`endif
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`OR1200_ALUOP_ADD : begin
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`OR1200_ALUOP_ADD : begin
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cyforw = cy_sum;
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cyforw = cy_sum;
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cy_we = 1'b1;
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cy_we = 1'b1;
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end
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end
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`ifdef OR1200_IMPL_ADDC
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`OR1200_ALUOP_ADDC: begin
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cyforw = cy_csum;
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cy_we = 1'b1;
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end
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`endif
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`ifdef OR1200_IMPL_SUB
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`ifdef OR1200_IMPL_SUB
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`OR1200_ALUOP_SUB: begin
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`OR1200_ALUOP_SUB: begin
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cyforw = cy_sub;
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cyforw = cy_sub;
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cy_we = 1'b1;
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cy_we = 1'b1;
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end
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end
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Line 314... |
cy_we = 1'b0;
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cy_we = 1'b0;
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end
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end
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endcase
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endcase
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end
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end
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//
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// Generate SR[OV] write enable
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//
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always @(alu_op or ov_sum) begin
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casez (alu_op) // synopsys parallel_case
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`ifdef OR1200_IMPL_OV
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`ifdef OR1200_IMPL_ADDC
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`OR1200_ALUOP_ADDC,
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`endif
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`ifdef OR1200_IMPL_SUB
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`OR1200_ALUOP_SUB,
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`endif
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`OR1200_ALUOP_ADD : begin
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ovforw = ov_sum;
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ov_we = 1'b1;
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end
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`endif
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default: begin
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ovforw = 1'b0;
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ov_we = 1'b0;
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end
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endcase
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end
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//
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//
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// Shifts and rotation
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// Shifts and rotation
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//
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//
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always @(alu_op2 or a or b) begin
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always @(alu_op2 or a or b) begin
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case (alu_op2) // synopsys parallel_case
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case (alu_op2) // synopsys parallel_case
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