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//////////////////////////////////////////////////////////////////////
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//// ////
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//// OR1200's CPU ////
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//// ////
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//// This file is part of the OpenRISC 1200 project ////
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//// http://www.opencores.org/project,or1k ////
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//// ////
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//// Description ////
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//// Instantiation of internal CPU blocks. IFETCH, SPRS, FRZ, ////
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//// ALU, EXCEPT, ID, WBMUX, OPERANDMUX, RF etc. ////
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//// ////
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//// To Do: ////
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//// - make it smaller and faster ////
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//// ////
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//// Author(s): ////
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//// - Damjan Lampret, lampret@opencores.org ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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// $Log: or1200_cpu.v,v $
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// Revision 2.0 2010/06/30 11:00:00 ORSoC
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// Major update:
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// Structure reordered and bugs fixed.
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// synopsys translate_off
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`include "timescale.v"
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// synopsys translate_on
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`include "or1200_defines.v"
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module or1200_cpu(
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// Clk & Rst
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clk, rst,
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// Insn interface
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ic_en,
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icpu_adr_o, icpu_cycstb_o, icpu_sel_o, icpu_tag_o,
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icpu_dat_i, icpu_ack_i, icpu_rty_i, icpu_err_i, icpu_adr_i, icpu_tag_i,
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immu_en,
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// Debug unit
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id_void, id_insn, ex_void,
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ex_insn, ex_freeze, wb_insn, wb_freeze, id_pc, ex_pc, wb_pc, branch_op,
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spr_dat_npc, rf_dataw, ex_flushpipe,
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du_stall, du_addr, du_dat_du, du_read, du_write, du_except_stop,
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du_except_trig, du_dsr, du_dmr1, du_hwbkpt, du_hwbkpt_ls_r, du_dat_cpu,
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du_lsu_store_dat, du_lsu_load_dat,
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abort_mvspr, abort_ex,
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// Data interface
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dc_en,
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dcpu_adr_o, dcpu_cycstb_o, dcpu_we_o, dcpu_sel_o, dcpu_tag_o,
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dcpu_dat_o, dcpu_dat_i, dcpu_ack_i, dcpu_rty_i, dcpu_err_i, dcpu_tag_i,
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sb_en, dmmu_en, dc_no_writethrough,
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// SR Interface
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boot_adr_sel_i,
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// Interrupt & tick exceptions
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sig_int, sig_tick,
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// SPR interface
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supv, spr_addr, spr_dat_cpu, spr_dat_pic, spr_dat_tt, spr_dat_pm,
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spr_dat_dmmu, spr_dat_immu, spr_dat_du, spr_cs, spr_we, mtspr_dc_done
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);
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parameter dw = `OR1200_OPERAND_WIDTH;
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parameter aw = `OR1200_REGFILE_ADDR_WIDTH;
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//
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// I/O ports
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//
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//
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// Clk & Rst
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//
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input clk;
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input rst;
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//
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// Insn (IC) interface
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//
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output ic_en;
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output [31:0] icpu_adr_o;
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output icpu_cycstb_o;
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output [3:0] icpu_sel_o;
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output [3:0] icpu_tag_o;
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input [31:0] icpu_dat_i;
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input icpu_ack_i;
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input icpu_rty_i;
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input icpu_err_i;
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input [31:0] icpu_adr_i;
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input [3:0] icpu_tag_i;
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//
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// Insn (IMMU) interface
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//
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output immu_en;
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//
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// Debug interface
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//
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output id_void;
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output [31:0] id_insn;
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output ex_void;
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output [31:0] ex_insn;
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output ex_freeze;
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output [31:0] wb_insn;
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output wb_freeze;
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output [31:0] id_pc;
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output [31:0] ex_pc;
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output [31:0] wb_pc;
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output ex_flushpipe;
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output [`OR1200_BRANCHOP_WIDTH-1:0] branch_op;
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input du_stall;
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input [dw-1:0] du_addr;
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input [dw-1:0] du_dat_du;
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input du_read;
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input du_write;
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input [`OR1200_DU_DSR_WIDTH-1:0] du_dsr;
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input [24:0] du_dmr1;
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input du_hwbkpt;
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input du_hwbkpt_ls_r;
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output [13:0] du_except_trig;
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output [13:0] du_except_stop;
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output [dw-1:0] du_dat_cpu;
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output [dw-1:0] rf_dataw;
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output [dw-1:0] du_lsu_store_dat;
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output [dw-1:0] du_lsu_load_dat;
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//
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// Data (DC) interface
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//
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output [31:0] dcpu_adr_o;
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output dcpu_cycstb_o;
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output dcpu_we_o;
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output [3:0] dcpu_sel_o;
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output [3:0] dcpu_tag_o;
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output [31:0] dcpu_dat_o;
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input [31:0] dcpu_dat_i;
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input dcpu_ack_i;
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input dcpu_rty_i;
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input dcpu_err_i;
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input [3:0] dcpu_tag_i;
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output dc_en;
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output dc_no_writethrough;
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//
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// Data (DMMU) interface
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//
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output sb_en;
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output dmmu_en;
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output abort_ex;
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output abort_mvspr;
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//
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// SR Interface
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//
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input boot_adr_sel_i;
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//
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// SPR interface
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//
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output supv;
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input [dw-1:0] spr_dat_pic;
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input [dw-1:0] spr_dat_tt;
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input [dw-1:0] spr_dat_pm;
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input [dw-1:0] spr_dat_dmmu;
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input [dw-1:0] spr_dat_immu;
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input [dw-1:0] spr_dat_du;
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output [dw-1:0] spr_addr;
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output [dw-1:0] spr_dat_cpu;
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output [dw-1:0] spr_dat_npc;
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output [31:0] spr_cs;
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output spr_we;
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input mtspr_dc_done;
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//
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// Interrupt exceptions
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//
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input sig_int;
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input sig_tick;
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//
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// Internal wires
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//
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wire [31:0] if_insn;
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wire saving_if_insn;
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wire [31:0] if_pc;
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wire [aw-1:0] rf_addrw;
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wire [aw-1:0] rf_addra;
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wire [aw-1:0] rf_addrb;
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wire rf_rda;
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wire rf_rdb;
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wire [dw-1:0] id_simm;
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wire [dw-1:2] id_branch_addrtarget;
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wire [dw-1:2] ex_branch_addrtarget;
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wire [`OR1200_ALUOP_WIDTH-1:0] alu_op;
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wire [`OR1200_SHROTOP_WIDTH-1:0] shrot_op;
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wire [`OR1200_COMPOP_WIDTH-1:0] comp_op;
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wire [`OR1200_BRANCHOP_WIDTH-1:0] pre_branch_op;
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wire [`OR1200_BRANCHOP_WIDTH-1:0] branch_op;
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wire [`OR1200_LSUOP_WIDTH-1:0] id_lsu_op;
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wire genpc_freeze;
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wire if_freeze;
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wire id_freeze;
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wire ex_freeze;
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wire wb_freeze;
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wire [`OR1200_SEL_WIDTH-1:0] sel_a;
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wire [`OR1200_SEL_WIDTH-1:0] sel_b;
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wire [`OR1200_RFWBOP_WIDTH-1:0] rfwb_op;
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wire [`OR1200_FPUOP_WIDTH-1:0] fpu_op;
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wire [dw-1:0] rf_dataw;
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wire [dw-1:0] rf_dataa;
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wire [dw-1:0] rf_datab;
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wire [dw-1:0] muxed_a;
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wire [dw-1:0] muxed_b;
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wire [dw-1:0] wb_forw;
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wire wbforw_valid;
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wire [dw-1:0] operand_a;
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wire [dw-1:0] operand_b;
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wire [dw-1:0] alu_dataout;
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wire [dw-1:0] lsu_dataout;
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wire [dw-1:0] sprs_dataout;
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wire [dw-1:0] fpu_dataout;
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wire fpu_done;
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wire [31:0] ex_simm;
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wire [`OR1200_MULTICYCLE_WIDTH-1:0] multicycle;
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wire [`OR1200_WAIT_ON_WIDTH-1:0] wait_on;
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wire [`OR1200_EXCEPT_WIDTH-1:0] except_type;
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wire [4:0] cust5_op;
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wire [5:0] cust5_limm;
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wire if_flushpipe;
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wire id_flushpipe;
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wire ex_flushpipe;
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wire wb_flushpipe;
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wire extend_flush;
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wire ex_branch_taken;
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wire flag;
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wire flagforw;
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wire flag_we;
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wire flagforw_alu;
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wire flag_we_alu;
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wire flagforw_fpu;
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wire flag_we_fpu;
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wire carry;
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wire cyforw;
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wire cy_we_alu;
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wire cy_we_rf;
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wire lsu_stall;
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wire epcr_we;
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wire eear_we;
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wire esr_we;
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wire pc_we;
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wire [31:0] epcr;
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wire [31:0] eear;
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wire [`OR1200_SR_WIDTH-1:0] esr;
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wire [`OR1200_FPCSR_WIDTH-1:0] fpcsr;
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wire fpcsr_we;
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wire sr_we;
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wire [`OR1200_SR_WIDTH-1:0] to_sr;
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wire [`OR1200_SR_WIDTH-1:0] sr;
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wire except_flushpipe;
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wire except_start;
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wire except_started;
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wire fpu_except_started;
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wire [31:0] wb_insn;
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wire sig_syscall;
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wire sig_trap;
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wire sig_fp;
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wire [31:0] spr_dat_cfgr;
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wire [31:0] spr_dat_rf;
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wire [31:0] spr_dat_npc;
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wire [31:0] spr_dat_ppc;
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wire [31:0] spr_dat_mac;
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wire [31:0] spr_dat_fpu;
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wire mtspr_done;
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wire force_dslot_fetch;
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wire no_more_dslot;
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wire ex_void;
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wire ex_spr_read;
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wire ex_spr_write;
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wire if_stall;
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wire id_macrc_op;
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wire ex_macrc_op;
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wire [`OR1200_MACOP_WIDTH-1:0] id_mac_op;
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wire [`OR1200_MACOP_WIDTH-1:0] mac_op;
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wire [31:0] mult_mac_result;
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wire mac_stall;
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wire [13:0] except_trig;
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wire [13:0] except_stop;
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wire genpc_refetch;
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wire rfe;
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wire lsu_unstall;
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wire except_align;
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wire except_dtlbmiss;
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wire except_dmmufault;
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wire except_illegal;
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wire except_itlbmiss;
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wire except_immufault;
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wire except_ibuserr;
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wire except_dbuserr;
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wire abort_ex;
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wire abort_mvspr;
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//
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// Send exceptions to Debug Unit
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//
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assign du_except_trig = except_trig;
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assign du_except_stop = except_stop;
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assign du_lsu_store_dat = operand_b;
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assign du_lsu_load_dat = lsu_dataout;
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//
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// Data cache enable
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//
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`ifdef OR1200_NO_DC
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assign dc_en = 1'b0;
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`else
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assign dc_en = sr[`OR1200_SR_DCE];
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`endif
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//
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// Instruction cache enable
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//
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`ifdef OR1200_NO_IC
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assign ic_en = 1'b0;
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`else
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assign ic_en = sr[`OR1200_SR_ICE];
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`endif
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//
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// SB enable
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//
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`ifdef OR1200_SB_IMPLEMENTED
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//assign sb_en = sr[`OR1200_SR_SBE]; // SBE not defined -- jb
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`else
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assign sb_en = 1'b0;
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`endif
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//
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// DMMU enable
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//
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`ifdef OR1200_NO_DMMU
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assign dmmu_en = 1'b0;
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`else
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assign dmmu_en = sr[`OR1200_SR_DME];
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`endif
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//
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// IMMU enable
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//
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`ifdef OR1200_NO_IMMU
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assign immu_en = 1'b0;
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`else
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assign immu_en = sr[`OR1200_SR_IME] & ~except_started;
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`endif
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//
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// SUPV bit
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//
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assign supv = sr[`OR1200_SR_SM];
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//
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// FLAG write enable
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//
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assign flagforw = (flag_we_alu & flagforw_alu) | (flagforw_fpu & flag_we_fpu);
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assign flag_we = (flag_we_alu | flag_we_fpu) & ~abort_mvspr;
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//
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// Flag for any MTSPR instructions, that must block execution, to indicate done
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//
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assign mtspr_done = mtspr_dc_done;
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//
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// Instantiation of instruction fetch block
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//
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or1200_genpc or1200_genpc(
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.clk(clk),
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.rst(rst),
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.icpu_adr_o(icpu_adr_o),
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.icpu_cycstb_o(icpu_cycstb_o),
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.icpu_sel_o(icpu_sel_o),
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.icpu_tag_o(icpu_tag_o),
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.icpu_rty_i(icpu_rty_i),
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.icpu_adr_i(icpu_adr_i),
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.pre_branch_op(pre_branch_op),
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.branch_op(branch_op),
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.except_type(except_type),
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.except_start(except_start),
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.except_prefix(sr[`OR1200_SR_EPH]),
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.id_branch_addrtarget(id_branch_addrtarget),
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.ex_branch_addrtarget(ex_branch_addrtarget),
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.muxed_b(muxed_b),
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.operand_b(operand_b),
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.flag(flag),
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.flagforw(flagforw),
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.ex_branch_taken(ex_branch_taken),
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.epcr(epcr),
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.spr_dat_i(spr_dat_cpu),
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.spr_pc_we(pc_we),
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.genpc_refetch(genpc_refetch),
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.genpc_freeze(genpc_freeze),
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.no_more_dslot(no_more_dslot)
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);
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//
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// Instantiation of instruction fetch block
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//
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or1200_if or1200_if(
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.clk(clk),
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.rst(rst),
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.icpu_dat_i(icpu_dat_i),
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.icpu_ack_i(icpu_ack_i),
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.icpu_err_i(icpu_err_i),
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.icpu_adr_i(icpu_adr_i),
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.icpu_tag_i(icpu_tag_i),
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|
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.if_freeze(if_freeze),
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.if_insn(if_insn),
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.if_pc(if_pc),
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.saving_if_insn(saving_if_insn),
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.if_flushpipe(if_flushpipe),
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.if_stall(if_stall),
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.no_more_dslot(no_more_dslot),
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.genpc_refetch(genpc_refetch),
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.rfe(rfe),
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.except_itlbmiss(except_itlbmiss),
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.except_immufault(except_immufault),
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.except_ibuserr(except_ibuserr)
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);
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//
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// Instantiation of instruction decode/control logic
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//
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or1200_ctrl or1200_ctrl(
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.clk(clk),
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.rst(rst),
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.id_freeze(id_freeze),
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.ex_freeze(ex_freeze),
|
|
.wb_freeze(wb_freeze),
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.if_flushpipe(if_flushpipe),
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.id_flushpipe(id_flushpipe),
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.ex_flushpipe(ex_flushpipe),
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.wb_flushpipe(wb_flushpipe),
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.extend_flush(extend_flush),
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.except_flushpipe(except_flushpipe),
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|
.abort_mvspr(abort_mvspr),
|
|
.if_insn(if_insn),
|
|
.id_insn(id_insn),
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|
.ex_insn(ex_insn),
|
|
.id_branch_op(pre_branch_op),
|
|
.ex_branch_op(branch_op),
|
|
.ex_branch_taken(ex_branch_taken),
|
|
.rf_addra(rf_addra),
|
|
.rf_addrb(rf_addrb),
|
|
.rf_rda(rf_rda),
|
|
.rf_rdb(rf_rdb),
|
|
.alu_op(alu_op),
|
|
.mac_op(mac_op),
|
|
.shrot_op(shrot_op),
|
|
.comp_op(comp_op),
|
|
.rf_addrw(rf_addrw),
|
|
.rfwb_op(rfwb_op),
|
|
.fpu_op(fpu_op),
|
|
.pc_we(pc_we),
|
|
.wb_insn(wb_insn),
|
|
.id_simm(id_simm),
|
|
.id_branch_addrtarget(id_branch_addrtarget),
|
|
.ex_branch_addrtarget(ex_branch_addrtarget),
|
|
.ex_simm(ex_simm),
|
|
.sel_a(sel_a),
|
|
.sel_b(sel_b),
|
|
.id_lsu_op(id_lsu_op),
|
|
.cust5_op(cust5_op),
|
|
.cust5_limm(cust5_limm),
|
|
.id_pc(id_pc),
|
|
.ex_pc(ex_pc),
|
|
.multicycle(multicycle),
|
|
.wait_on(wait_on),
|
|
.wbforw_valid(wbforw_valid),
|
|
.sig_syscall(sig_syscall),
|
|
.sig_trap(sig_trap),
|
|
.force_dslot_fetch(force_dslot_fetch),
|
|
.no_more_dslot(no_more_dslot),
|
|
.id_void(id_void),
|
|
.ex_void(ex_void),
|
|
.ex_spr_read(ex_spr_read),
|
|
.ex_spr_write(ex_spr_write),
|
|
.id_mac_op(id_mac_op),
|
|
.id_macrc_op(id_macrc_op),
|
|
.ex_macrc_op(ex_macrc_op),
|
|
.rfe(rfe),
|
|
.du_hwbkpt(du_hwbkpt),
|
|
.except_illegal(except_illegal),
|
|
.dc_no_writethrough(dc_no_writethrough)
|
|
);
|
|
|
|
//
|
|
// Instantiation of register file
|
|
//
|
|
or1200_rf or1200_rf(
|
|
.clk(clk),
|
|
.rst(rst),
|
|
.cy_we_i(cy_we_alu),
|
|
.cy_we_o(cy_we_rf),
|
|
.supv(sr[`OR1200_SR_SM]),
|
|
.wb_freeze(wb_freeze),
|
|
.addrw(rf_addrw),
|
|
.dataw(rf_dataw),
|
|
.id_freeze(id_freeze),
|
|
.we(rfwb_op[0]),
|
|
.flushpipe(wb_flushpipe),
|
|
.addra(rf_addra),
|
|
.rda(rf_rda),
|
|
.dataa(rf_dataa),
|
|
.addrb(rf_addrb),
|
|
.rdb(rf_rdb),
|
|
.datab(rf_datab),
|
|
.spr_cs(spr_cs[`OR1200_SPR_GROUP_SYS]),
|
|
.spr_write(spr_we),
|
|
.spr_addr(spr_addr),
|
|
.spr_dat_i(spr_dat_cpu),
|
|
.spr_dat_o(spr_dat_rf),
|
|
.du_read(du_read)
|
|
);
|
|
|
|
//
|
|
// Instantiation of operand muxes
|
|
//
|
|
or1200_operandmuxes or1200_operandmuxes(
|
|
.clk(clk),
|
|
.rst(rst),
|
|
.id_freeze(id_freeze),
|
|
.ex_freeze(ex_freeze),
|
|
.rf_dataa(rf_dataa),
|
|
.rf_datab(rf_datab),
|
|
.ex_forw(rf_dataw),
|
|
.wb_forw(wb_forw),
|
|
.simm(id_simm),
|
|
.sel_a(sel_a),
|
|
.sel_b(sel_b),
|
|
.operand_a(operand_a),
|
|
.operand_b(operand_b),
|
|
.muxed_a(muxed_a),
|
|
.muxed_b(muxed_b)
|
|
);
|
|
|
|
//
|
|
// Instantiation of CPU's ALU
|
|
//
|
|
or1200_alu or1200_alu(
|
|
.a(operand_a),
|
|
.b(operand_b),
|
|
.mult_mac_result(mult_mac_result),
|
|
.macrc_op(ex_macrc_op),
|
|
.alu_op(alu_op),
|
|
.shrot_op(shrot_op),
|
|
.comp_op(comp_op),
|
|
.cust5_op(cust5_op),
|
|
.cust5_limm(cust5_limm),
|
|
.result(alu_dataout),
|
|
.flagforw(flagforw_alu),
|
|
.flag_we(flag_we_alu),
|
|
.cyforw(cyforw),
|
|
.cy_we(cy_we_alu),
|
|
.flag(flag),
|
|
.carry(carry)
|
|
);
|
|
|
|
|
|
//
|
|
// FPU's exception is being dealt with
|
|
//
|
|
assign fpu_except_started = except_started && (except_type == `OR1200_EXCEPT_FLOAT);
|
|
|
|
//
|
|
// Instantiation of FPU
|
|
//
|
|
or1200_fpu or1200_fpu(
|
|
.clk(clk),
|
|
.rst(rst),
|
|
.ex_freeze(ex_freeze),
|
|
.a(operand_a),
|
|
.b(operand_b),
|
|
.fpu_op(fpu_op),
|
|
.result(fpu_dataout),
|
|
.done(fpu_done),
|
|
.flagforw(flagforw_fpu),
|
|
.flag_we(flag_we_fpu),
|
|
.sig_fp(sig_fp),
|
|
.except_started(fpu_except_started),
|
|
.fpcsr_we(fpcsr_we),
|
|
.fpcsr(fpcsr),
|
|
.spr_cs(spr_cs[`OR1200_SPR_GROUP_FPU]),
|
|
.spr_write(spr_we),
|
|
.spr_addr(spr_addr),
|
|
.spr_dat_i(spr_dat_cpu),
|
|
.spr_dat_o(spr_dat_fpu)
|
|
);
|
|
|
|
|
|
//
|
|
// Instantiation of CPU's multiply unit
|
|
//
|
|
or1200_mult_mac or1200_mult_mac(
|
|
.clk(clk),
|
|
.rst(rst),
|
|
.ex_freeze(ex_freeze),
|
|
.id_macrc_op(id_macrc_op),
|
|
.macrc_op(ex_macrc_op),
|
|
.a(operand_a),
|
|
.b(operand_b),
|
|
.mac_op(mac_op),
|
|
.alu_op(alu_op),
|
|
.result(mult_mac_result),
|
|
.mac_stall_r(mac_stall),
|
|
.spr_cs(spr_cs[`OR1200_SPR_GROUP_MAC]),
|
|
.spr_write(spr_we),
|
|
.spr_addr(spr_addr),
|
|
.spr_dat_i(spr_dat_cpu),
|
|
.spr_dat_o(spr_dat_mac)
|
|
);
|
|
|
|
//
|
|
// Instantiation of CPU's SPRS block
|
|
//
|
|
or1200_sprs or1200_sprs(
|
|
.clk(clk),
|
|
.rst(rst),
|
|
.addrbase(operand_a),
|
|
.addrofs(ex_simm[15:0]),
|
|
.dat_i(operand_b),
|
|
.ex_spr_read(ex_spr_read),
|
|
.ex_spr_write(ex_spr_write),
|
|
.flagforw(flagforw),
|
|
.flag_we(flag_we),
|
|
.flag(flag),
|
|
.cyforw(cyforw),
|
|
.cy_we(cy_we_rf),
|
|
.carry(carry),
|
|
.to_wbmux(sprs_dataout),
|
|
|
|
.du_addr(du_addr),
|
|
.du_dat_du(du_dat_du),
|
|
.du_read(du_read),
|
|
.du_write(du_write),
|
|
.du_dat_cpu(du_dat_cpu),
|
|
.boot_adr_sel_i(boot_adr_sel_i),
|
|
.spr_addr(spr_addr),
|
|
.spr_dat_pic(spr_dat_pic),
|
|
.spr_dat_tt(spr_dat_tt),
|
|
.spr_dat_pm(spr_dat_pm),
|
|
.spr_dat_cfgr(spr_dat_cfgr),
|
|
.spr_dat_rf(spr_dat_rf),
|
|
.spr_dat_npc(spr_dat_npc),
|
|
.spr_dat_ppc(spr_dat_ppc),
|
|
.spr_dat_mac(spr_dat_mac),
|
|
.spr_dat_dmmu(spr_dat_dmmu),
|
|
.spr_dat_immu(spr_dat_immu),
|
|
.spr_dat_du(spr_dat_du),
|
|
.spr_dat_o(spr_dat_cpu),
|
|
.spr_cs(spr_cs),
|
|
.spr_we(spr_we),
|
|
|
|
.epcr_we(epcr_we),
|
|
.eear_we(eear_we),
|
|
.esr_we(esr_we),
|
|
.pc_we(pc_we),
|
|
.epcr(epcr),
|
|
.eear(eear),
|
|
.esr(esr),
|
|
.except_started(except_started),
|
|
|
|
.fpcsr(fpcsr),
|
|
.fpcsr_we(fpcsr_we),
|
|
.spr_dat_fpu(spr_dat_fpu),
|
|
|
|
.sr_we(sr_we),
|
|
.to_sr(to_sr),
|
|
.sr(sr),
|
|
.branch_op(branch_op)
|
|
);
|
|
|
|
//
|
|
// Instantiation of load/store unit
|
|
//
|
|
or1200_lsu or1200_lsu(
|
|
.clk(clk),
|
|
.rst(rst),
|
|
.id_addrbase(muxed_a),
|
|
.id_addrofs(id_simm),
|
|
.ex_addrbase(operand_a),
|
|
.ex_addrofs(ex_simm),
|
|
.id_lsu_op(id_lsu_op),
|
|
.lsu_datain(operand_b),
|
|
.lsu_dataout(lsu_dataout),
|
|
.lsu_stall(lsu_stall),
|
|
.lsu_unstall(lsu_unstall),
|
|
.du_stall(du_stall),
|
|
.except_align(except_align),
|
|
.except_dtlbmiss(except_dtlbmiss),
|
|
.except_dmmufault(except_dmmufault),
|
|
.except_dbuserr(except_dbuserr),
|
|
.id_freeze(id_freeze),
|
|
.ex_freeze(ex_freeze),
|
|
.flushpipe(ex_flushpipe),
|
|
|
|
.dcpu_adr_o(dcpu_adr_o),
|
|
.dcpu_cycstb_o(dcpu_cycstb_o),
|
|
.dcpu_we_o(dcpu_we_o),
|
|
.dcpu_sel_o(dcpu_sel_o),
|
|
.dcpu_tag_o(dcpu_tag_o),
|
|
.dcpu_dat_o(dcpu_dat_o),
|
|
.dcpu_dat_i(dcpu_dat_i),
|
|
.dcpu_ack_i(dcpu_ack_i),
|
|
.dcpu_rty_i(dcpu_rty_i),
|
|
.dcpu_err_i(dcpu_err_i),
|
|
.dcpu_tag_i(dcpu_tag_i)
|
|
);
|
|
|
|
//
|
|
// Instantiation of write-back muxes
|
|
//
|
|
or1200_wbmux or1200_wbmux(
|
|
.clk(clk),
|
|
.rst(rst),
|
|
.wb_freeze(wb_freeze),
|
|
.rfwb_op(rfwb_op),
|
|
.muxin_a(alu_dataout),
|
|
.muxin_b(lsu_dataout),
|
|
.muxin_c(sprs_dataout),
|
|
.muxin_d(ex_pc),
|
|
.muxin_e(fpu_dataout),
|
|
.muxout(rf_dataw),
|
|
.muxreg(wb_forw),
|
|
.muxreg_valid(wbforw_valid)
|
|
);
|
|
|
|
//
|
|
// Instantiation of freeze logic
|
|
//
|
|
or1200_freeze or1200_freeze(
|
|
.clk(clk),
|
|
.rst(rst),
|
|
.multicycle(multicycle),
|
|
.wait_on(wait_on),
|
|
.fpu_done(fpu_done),
|
|
.mtspr_done(mtspr_done),
|
|
.flushpipe(wb_flushpipe),
|
|
.extend_flush(extend_flush),
|
|
.lsu_stall(lsu_stall),
|
|
.if_stall(if_stall),
|
|
.lsu_unstall(lsu_unstall),
|
|
.force_dslot_fetch(force_dslot_fetch),
|
|
.abort_ex(abort_ex),
|
|
.du_stall(du_stall),
|
|
.mac_stall(mac_stall),
|
|
.saving_if_insn(saving_if_insn),
|
|
.genpc_freeze(genpc_freeze),
|
|
.if_freeze(if_freeze),
|
|
.id_freeze(id_freeze),
|
|
.ex_freeze(ex_freeze),
|
|
.wb_freeze(wb_freeze),
|
|
.icpu_ack_i(icpu_ack_i),
|
|
.icpu_err_i(icpu_err_i)
|
|
);
|
|
|
|
//
|
|
// Instantiation of exception block
|
|
//
|
|
or1200_except or1200_except(
|
|
.clk(clk),
|
|
.rst(rst),
|
|
.sig_ibuserr(except_ibuserr),
|
|
.sig_dbuserr(except_dbuserr),
|
|
.sig_illegal(except_illegal),
|
|
.sig_align(except_align),
|
|
.sig_range(1'b0),
|
|
.sig_dtlbmiss(except_dtlbmiss),
|
|
.sig_dmmufault(except_dmmufault),
|
|
.sig_int(sig_int),
|
|
.sig_syscall(sig_syscall),
|
|
.sig_trap(sig_trap),
|
|
.sig_itlbmiss(except_itlbmiss),
|
|
.sig_immufault(except_immufault),
|
|
.sig_tick(sig_tick),
|
|
.sig_fp(sig_fp),
|
|
.fpcsr_fpee(fpcsr[`OR1200_FPCSR_FPEE]),
|
|
.ex_branch_taken(ex_branch_taken),
|
|
.icpu_ack_i(icpu_ack_i),
|
|
.icpu_err_i(icpu_err_i),
|
|
.dcpu_ack_i(dcpu_ack_i),
|
|
.dcpu_err_i(dcpu_err_i),
|
|
.genpc_freeze(genpc_freeze),
|
|
.id_freeze(id_freeze),
|
|
.ex_freeze(ex_freeze),
|
|
.wb_freeze(wb_freeze),
|
|
.if_stall(if_stall),
|
|
.if_pc(if_pc),
|
|
.id_pc(id_pc),
|
|
.ex_pc(ex_pc),
|
|
.wb_pc(wb_pc),
|
|
.id_flushpipe(id_flushpipe),
|
|
.ex_flushpipe(ex_flushpipe),
|
|
.extend_flush(extend_flush),
|
|
.except_flushpipe(except_flushpipe),
|
|
.abort_mvspr(abort_mvspr),
|
|
.except_type(except_type),
|
|
.except_start(except_start),
|
|
.except_started(except_started),
|
|
.except_stop(except_stop),
|
|
.except_trig(except_trig),
|
|
.ex_void(ex_void),
|
|
.spr_dat_ppc(spr_dat_ppc),
|
|
.spr_dat_npc(spr_dat_npc),
|
|
|
|
.datain(spr_dat_cpu),
|
|
.branch_op(branch_op),
|
|
.du_dsr(du_dsr),
|
|
.du_dmr1(du_dmr1),
|
|
.du_hwbkpt(du_hwbkpt),
|
|
.du_hwbkpt_ls_r(du_hwbkpt_ls_r),
|
|
.epcr_we(epcr_we),
|
|
.eear_we(eear_we),
|
|
.esr_we(esr_we),
|
|
.pc_we(pc_we),
|
|
.epcr(epcr),
|
|
.eear(eear),
|
|
.esr(esr),
|
|
|
|
.lsu_addr(dcpu_adr_o),
|
|
.sr_we(sr_we),
|
|
.to_sr(to_sr),
|
|
.sr(sr),
|
|
.abort_ex(abort_ex)
|
|
);
|
|
|
|
//
|
|
// Instantiation of configuration registers
|
|
//
|
|
or1200_cfgr or1200_cfgr(
|
|
.spr_addr(spr_addr),
|
|
.spr_dat_o(spr_dat_cfgr)
|
|
);
|
|
|
|
endmodule
|
|
|
No newline at end of file
|
No newline at end of file
|
