URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [or1200/] [or1200_cpu.v] - Diff between revs 435 and 483

Rev 435	Rev 483
Line 84...	Line 84...
`sig_int, sig_tick,`	`sig_int, sig_tick,`

`// SPR interface`	`// SPR interface`
`supv, spr_addr, spr_dat_cpu, spr_dat_pic, spr_dat_tt, spr_dat_pm,`	`supv, spr_addr, spr_dat_cpu, spr_dat_pic, spr_dat_tt, spr_dat_pm,`
`spr_dat_dmmu, spr_dat_immu, spr_dat_du, spr_cs, spr_we, mtspr_dc_done`	`spr_dat_dmmu, spr_dat_immu, spr_dat_du, spr_cs, spr_we, mtspr_dc_done`

	`ifdef OR1200_RAM_PARITY
	`,p_err_rf`
	`endif

`);`	`);`

parameter dw = `OR1200_OPERAND_WIDTH;	parameter dw = `OR1200_OPERAND_WIDTH;
parameter aw = `OR1200_REGFILE_ADDR_WIDTH;	parameter aw = `OR1200_REGFILE_ADDR_WIDTH;

Line 205...	Line 210...
`//`	`//`
`input sig_int;`	`input sig_int;`
`input sig_tick;`	`input sig_tick;`

`//`	`//`
	`// Register file parity error indicator`
	`//`
	`ifdef OR1200_RAM_PARITY
	`output p_err_rf;`
	`endif


	`//`
`// Internal wires`	`// Internal wires`
`//`	`//`
`wire [31:0] if_insn;`	`wire [31:0] if_insn;`
`wire saving_if_insn;`	`wire saving_if_insn;`
`wire [31:0] if_pc;`	`wire [31:0] if_pc;`
Line 529...	Line 542...
`// Instantiation of register file`	`// Instantiation of register file`
`//`	`//`
`or1200_rf or1200_rf(`	`or1200_rf or1200_rf(`
`.clk(clk),`	`.clk(clk),`
`.rst(rst),`	`.rst(rst),`
	`ifdef OR1200_RAM_PARITY
	`.p_err(p_err_rf),`
	`endif
`.cy_we_i(cy_we_alu),`	`.cy_we_i(cy_we_alu),`
`.cy_we_o(cy_we_rf),`	`.cy_we_o(cy_we_rf),`
.supv(sr[`OR1200_SR_SM]),	.supv(sr[`OR1200_SR_SM]),
`.wb_freeze(wb_freeze),`	`.wb_freeze(wb_freeze),`
`.addrw(rf_addrw),`	`.addrw(rf_addrw),`