Line 319... |
Line 319... |
//
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//
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// pipeline ID and EX branch target address
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// pipeline ID and EX branch target address
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always @(posedge clk or `OR1200_RST_EVENT rst) begin
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always @(posedge clk or `OR1200_RST_EVENT rst) begin
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if (rst == `OR1200_RST_VALUE)
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if (rst == `OR1200_RST_VALUE)
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ex_branch_addrtarget <= 32'h00000000;
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ex_branch_addrtarget <= 0;
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else if (!ex_freeze)
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else if (!ex_freeze)
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ex_branch_addrtarget <= id_branch_addrtarget;
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ex_branch_addrtarget <= id_branch_addrtarget;
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end
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end
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// not pipelined
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// not pipelined
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//assign ex_branch_addrtarget = {{4{ex_insn[25]}}, ex_insn[25:0]} + ex_pc[31:2];
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//assign ex_branch_addrtarget = {{4{ex_insn[25]}}, ex_insn[25:0]} + ex_pc[31:2];
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Line 469... |
Line 469... |
multicycle = `OR1200_TWO_CYCLES; // to read from ITLB/DTLB (sync RAMs)
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multicycle = `OR1200_TWO_CYCLES; // to read from ITLB/DTLB (sync RAMs)
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// ALU instructions except the one with immediate
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// ALU instructions except the one with immediate
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`OR1200_OR32_ALU:
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`OR1200_OR32_ALU:
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case (id_insn[3:0]) // synopsys parallel_case
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case (id_insn[3:0]) // synopsys parallel_case
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4'h6: multicycle = 2'b11; // l.mul
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4'h6: multicycle = `OR1200_MULTICYCLE_WIDTH'd3; // l.mul
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4'h9: multicycle = 2'b10; // l.div
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4'h9: multicycle = `OR1200_MULTICYCLE_WIDTH'd2; // l.div
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4'hA: multicycle = 2'b10; // l.divu
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4'hA: multicycle = `OR1200_MULTICYCLE_WIDTH'd2; // l.divu
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4'hB: multicycle = 2'b11; // l.mulu
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4'hB: multicycle = `OR1200_MULTICYCLE_WIDTH'd3; // l.mulu
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default: multicycle = 2'b00;
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default: multicycle = `OR1200_MULTICYCLE_WIDTH'd0;
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endcase
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endcase
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`OR1200_OR32_MULI:
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`OR1200_OR32_MULI:
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multicycle = 2'h3;
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multicycle = `OR1200_MULTICYCLE_WIDTH'd3;
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// Single cycle instructions
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// Single cycle instructions
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default: begin
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default: begin
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multicycle = `OR1200_ONE_CYCLE;
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multicycle = `OR1200_ONE_CYCLE;
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end
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end
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Line 735... |
Line 734... |
except_illegal <= 1'b0
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except_illegal <= 1'b0
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`ifdef OR1200_MULT_IMPLEMENTED
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`ifdef OR1200_MULT_IMPLEMENTED
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`ifdef OR1200_DIV_IMPLEMENTED
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`ifdef OR1200_DIV_IMPLEMENTED
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`else
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`else
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| ({1'b0, id_insn[3:0]} == `OR1200_ALUOP_DIV)
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| (id_insn[3:0] == `OR1200_ALUOP_DIV)
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| ({1'b0, id_insn[3:0]} == `OR1200_ALUOP_DIVU)
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| (id_insn[3:0] == `OR1200_ALUOP_DIVU)
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`endif
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`endif
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`else
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`else
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| ({1'b0, id_insn[3:0]} == `OR1200_ALUOP_DIV)
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| (id_insn[3:0] == `OR1200_ALUOP_DIV)
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| ({1'b0, id_insn[3:0]} == `OR1200_ALUOP_DIVU)
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| (id_insn[3:0] == `OR1200_ALUOP_DIVU)
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| ({1'b0, id_insn[3:0]} == `OR1200_ALUOP_MUL)
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| (id_insn[3:0] == `OR1200_ALUOP_MUL)
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`endif
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`endif
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`ifdef OR1200_IMPL_ADDC
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`ifdef OR1200_IMPL_ADDC
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`else
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`else
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| ({1'b0, id_insn[3:0]} == `OR1200_ALUOP_ADDC)
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| (id_insn[3:0] == `OR1200_ALUOP_ADDC)
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`endif
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`endif
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`ifdef OR1200_IMPL_ALU_ROTATE
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`ifdef OR1200_IMPL_ALU_ROTATE
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`else
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`else
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| (({1'b0, id_insn[3:0]} == `OR1200_ALUOP_SHROT) && (id_insn[7:6] == `OR1200_SHROTOP_ROR))
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| ((id_insn[3:0] == `OR1200_ALUOP_SHROT) &
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(id_insn[7:6] == `OR1200_SHROTOP_ROR))
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`endif
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`endif
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`ifdef OR1200_IMPL_SUB
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`ifdef OR1200_IMPL_SUB
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`else
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`else
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| ({1'b0, id_insn[3:0]} == `OR1200_ALUOP_SUB)
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| (id_insn[3:0] == `OR1200_ALUOP_SUB)
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`endif
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`endif
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;
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;
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// Illegal and OR1200 unsupported instructions
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// Illegal and OR1200 unsupported instructions
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default:
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default:
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except_illegal <= 1'b1;
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except_illegal <= 1'b1;
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endcase
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endcase
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end // if (!ex_freeze)
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end
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end
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end
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//
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//
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// Decode of alu_op
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// Decode of alu_op
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//
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//
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always @(posedge clk or `OR1200_RST_EVENT rst) begin
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always @(posedge clk or `OR1200_RST_EVENT rst) begin
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if (rst == `OR1200_RST_VALUE)
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if (rst == `OR1200_RST_VALUE)
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