| Line 60... |
Line 60... |
// Internal i/f
|
// Internal i/f
|
except_flushpipe, extend_flush, if_flushpipe, id_flushpipe, ex_flushpipe,
|
except_flushpipe, extend_flush, if_flushpipe, id_flushpipe, ex_flushpipe,
|
wb_flushpipe,
|
wb_flushpipe,
|
id_freeze, ex_freeze, wb_freeze, if_insn, id_insn, ex_insn, abort_mvspr,
|
id_freeze, ex_freeze, wb_freeze, if_insn, id_insn, ex_insn, abort_mvspr,
|
id_branch_op, ex_branch_op, ex_branch_taken, pc_we,
|
id_branch_op, ex_branch_op, ex_branch_taken, pc_we,
|
rf_addra, rf_addrb, rf_rda, rf_rdb, alu_op, alu_op2, mac_op, shrot_op,
|
rf_addra, rf_addrb, rf_rda, rf_rdb, alu_op, alu_op2, mac_op,
|
comp_op, rf_addrw, rfwb_op, fpu_op,
|
comp_op, rf_addrw, rfwb_op, fpu_op,
|
wb_insn, id_simm, ex_simm, id_branch_addrtarget, ex_branch_addrtarget, sel_a,
|
wb_insn, id_simm, ex_simm, id_branch_addrtarget, ex_branch_addrtarget, sel_a,
|
sel_b, id_lsu_op,
|
sel_b, id_lsu_op,
|
cust5_op, cust5_limm, id_pc, ex_pc, du_hwbkpt,
|
cust5_op, cust5_limm, id_pc, ex_pc, du_hwbkpt,
|
multicycle, wait_on, wbforw_valid, sig_syscall, sig_trap,
|
multicycle, wait_on, wbforw_valid, sig_syscall, sig_trap,
|
| Line 100... |
Line 100... |
output rf_rda;
|
output rf_rda;
|
output rf_rdb;
|
output rf_rdb;
|
output [`OR1200_ALUOP_WIDTH-1:0] alu_op;
|
output [`OR1200_ALUOP_WIDTH-1:0] alu_op;
|
output [`OR1200_ALUOP2_WIDTH-1:0] alu_op2;
|
output [`OR1200_ALUOP2_WIDTH-1:0] alu_op2;
|
output [`OR1200_MACOP_WIDTH-1:0] mac_op;
|
output [`OR1200_MACOP_WIDTH-1:0] mac_op;
|
output [`OR1200_SHROTOP_WIDTH-1:0] shrot_op;
|
|
output [`OR1200_RFWBOP_WIDTH-1:0] rfwb_op;
|
output [`OR1200_RFWBOP_WIDTH-1:0] rfwb_op;
|
output [`OR1200_FPUOP_WIDTH-1:0] fpu_op;
|
output [`OR1200_FPUOP_WIDTH-1:0] fpu_op;
|
input pc_we;
|
input pc_we;
|
output [31:0] wb_insn;
|
output [31:0] wb_insn;
|
output [31:2] id_branch_addrtarget;
|
output [31:2] id_branch_addrtarget;
|
| Line 154... |
Line 153... |
reg ex_macrc_op;
|
reg ex_macrc_op;
|
`else
|
`else
|
wire [`OR1200_MACOP_WIDTH-1:0] mac_op;
|
wire [`OR1200_MACOP_WIDTH-1:0] mac_op;
|
wire ex_macrc_op;
|
wire ex_macrc_op;
|
`endif
|
`endif
|
reg [`OR1200_SHROTOP_WIDTH-1:0] shrot_op;
|
|
reg [31:0] id_insn /* verilator public */;
|
reg [31:0] id_insn /* verilator public */;
|
reg [31:0] ex_insn /* verilator public */;
|
reg [31:0] ex_insn /* verilator public */;
|
reg [31:0] wb_insn /* verilator public */;
|
reg [31:0] wb_insn /* verilator public */;
|
reg [`OR1200_REGFILE_ADDR_WIDTH-1:0] rf_addrw;
|
reg [`OR1200_REGFILE_ADDR_WIDTH-1:0] rf_addrw;
|
reg [`OR1200_REGFILE_ADDR_WIDTH-1:0] wb_rfaddrw;
|
reg [`OR1200_REGFILE_ADDR_WIDTH-1:0] wb_rfaddrw;
|
| Line 194... |
Line 192... |
assign rf_addrb = if_insn[15:11];
|
assign rf_addrb = if_insn[15:11];
|
assign rf_rda = if_insn[31] || if_maci_op;
|
assign rf_rda = if_insn[31] || if_maci_op;
|
assign rf_rdb = if_insn[30];
|
assign rf_rdb = if_insn[30];
|
|
|
//
|
//
|
// Force fetch of delay slot instruction when jump/branch is preceeded by load/store
|
// Force fetch of delay slot instruction when jump/branch is preceeded by
|
// instructions
|
// load/store instructions
|
//
|
//
|
assign force_dslot_fetch = 1'b0;
|
assign force_dslot_fetch = 1'b0;
|
assign no_more_dslot = (|ex_branch_op & !id_void & ex_branch_taken) | (ex_branch_op == `OR1200_BRANCHOP_RFE);
|
assign no_more_dslot = (|ex_branch_op & !id_void & ex_branch_taken) |
|
|
(ex_branch_op == `OR1200_BRANCHOP_RFE);
|
|
|
assign id_void = (id_insn[31:26] == `OR1200_OR32_NOP) & id_insn[16];
|
assign id_void = (id_insn[31:26] == `OR1200_OR32_NOP) & id_insn[16];
|
assign ex_void = (ex_insn[31:26] == `OR1200_OR32_NOP) & ex_insn[16];
|
assign ex_void = (ex_insn[31:26] == `OR1200_OR32_NOP) & ex_insn[16];
|
assign wb_void = (wb_insn[31:26] == `OR1200_OR32_NOP) & wb_insn[16];
|
assign wb_void = (wb_insn[31:26] == `OR1200_OR32_NOP) & wb_insn[16];
|
|
|
assign ex_spr_write = spr_write && !abort_mvspr;
|
assign ex_spr_write = spr_write && !abort_mvspr;
|
assign ex_spr_read = spr_read && !abort_mvspr;
|
assign ex_spr_read = spr_read && !abort_mvspr;
|
|
|
//
|
//
|
// ex_delayslot_dsi: delay slot insn is in EX stage
|
// ex_delayslot_dsi: delay slot insn is in EX stage
|
// ex_delayslot_nop: (filler) nop insn is in EX stage (before nops jump/branch was executed)
|
// ex_delayslot_nop: (filler) nop insn is in EX stage (before nops
|
|
// jump/branch was executed)
|
//
|
//
|
// ex_delayslot_dsi & !ex_delayslot_nop - DS insn in EX stage
|
// ex_delayslot_dsi & !ex_delayslot_nop - DS insn in EX stage
|
// !ex_delayslot_dsi & ex_delayslot_nop - NOP insn in EX stage,
|
// !ex_delayslot_dsi & ex_delayslot_nop - NOP insn in EX stage,
|
// next different is DS insn, previous different was Jump/Branch
|
// next different is DS insn, previous different was Jump/Branch
|
// !ex_delayslot_dsi & !ex_delayslot_nop - normal insn in EX stage
|
// !ex_delayslot_dsi & !ex_delayslot_nop - normal insn in EX stage
|
| Line 230... |
Line 230... |
else if (!ex_freeze & ex_delayslot_dsi & !ex_delayslot_nop) begin
|
else if (!ex_freeze & ex_delayslot_dsi & !ex_delayslot_nop) begin
|
ex_delayslot_nop <= 1'b0;
|
ex_delayslot_nop <= 1'b0;
|
ex_delayslot_dsi <= 1'b0;
|
ex_delayslot_dsi <= 1'b0;
|
end
|
end
|
else if (!ex_freeze) begin
|
else if (!ex_freeze) begin
|
ex_delayslot_nop <= id_void && ex_branch_taken && (ex_branch_op != `OR1200_BRANCHOP_NOP) &&
|
ex_delayslot_nop <= id_void && ex_branch_taken &&
|
|
(ex_branch_op != `OR1200_BRANCHOP_NOP) &&
|
(ex_branch_op != `OR1200_BRANCHOP_RFE);
|
(ex_branch_op != `OR1200_BRANCHOP_RFE);
|
ex_delayslot_dsi <= !id_void && ex_branch_taken && (ex_branch_op != `OR1200_BRANCHOP_NOP) &&
|
ex_delayslot_dsi <= !id_void && ex_branch_taken &&
|
|
(ex_branch_op != `OR1200_BRANCHOP_NOP) &&
|
(ex_branch_op != `OR1200_BRANCHOP_RFE);
|
(ex_branch_op != `OR1200_BRANCHOP_RFE);
|
end
|
end
|
end
|
end
|
|
|
//
|
//
|
| Line 271... |
Line 273... |
// l.addic
|
// l.addic
|
`OR1200_OR32_ADDIC:
|
`OR1200_OR32_ADDIC:
|
id_simm = {{16{id_insn[15]}}, id_insn[15:0]};
|
id_simm = {{16{id_insn[15]}}, id_insn[15:0]};
|
|
|
// l.lxx (load instructions)
|
// l.lxx (load instructions)
|
`OR1200_OR32_LWZ, `OR1200_OR32_LBZ, `OR1200_OR32_LBS, `OR1200_OR32_LHZ, `OR1200_OR32_LHS:
|
`OR1200_OR32_LWZ, `OR1200_OR32_LBZ, `OR1200_OR32_LBS,
|
|
`OR1200_OR32_LHZ, `OR1200_OR32_LHS:
|
id_simm = {{16{id_insn[15]}}, id_insn[15:0]};
|
id_simm = {{16{id_insn[15]}}, id_insn[15:0]};
|
|
|
// l.muli
|
// l.muli
|
`ifdef OR1200_MULT_IMPLEMENTED
|
`ifdef OR1200_MULT_IMPLEMENTED
|
`OR1200_OR32_MULI:
|
`OR1200_OR32_MULI:
|
| Line 283... |
Line 286... |
`endif
|
`endif
|
|
|
// l.maci
|
// l.maci
|
`ifdef OR1200_MAC_IMPLEMENTED
|
`ifdef OR1200_MAC_IMPLEMENTED
|
`OR1200_OR32_MACI:
|
`OR1200_OR32_MACI:
|
id_simm = {{16{id_insn[25]}}, id_insn[25:21], id_insn[10:0]};
|
id_simm = {{16{id_insn[15]}}, id_insn[15:0]};
|
`endif
|
`endif
|
|
|
// l.mtspr
|
// l.mtspr
|
`OR1200_OR32_MTSPR:
|
`OR1200_OR32_MTSPR:
|
id_simm = {16'b0, id_insn[25:21], id_insn[10:0]};
|
id_simm = {16'b0, id_insn[25:21], id_insn[10:0]};
|
| Line 341... |
Line 344... |
|
|
//
|
//
|
// l.macrc in ID stage
|
// l.macrc in ID stage
|
//
|
//
|
`ifdef OR1200_MAC_IMPLEMENTED
|
`ifdef OR1200_MAC_IMPLEMENTED
|
assign id_macrc_op = (id_insn[31:26] == `OR1200_OR32_MOVHI) & id_insn[16];
|
assign id_macrc_op = (id_insn[31:26] == `OR1200_OR32_MACRC) & id_insn[16];
|
`else
|
`else
|
assign id_macrc_op = 1'b0;
|
assign id_macrc_op = 1'b0;
|
`endif
|
`endif
|
|
|
//
|
//
|
| Line 371... |
Line 374... |
assign cust5_limm = ex_insn[10:5];
|
assign cust5_limm = ex_insn[10:5];
|
|
|
//
|
//
|
//
|
//
|
//
|
//
|
assign rfe = (id_branch_op == `OR1200_BRANCHOP_RFE) | (ex_branch_op == `OR1200_BRANCHOP_RFE);
|
assign rfe = (id_branch_op == `OR1200_BRANCHOP_RFE) |
|
|
(ex_branch_op == `OR1200_BRANCHOP_RFE);
|
|
|
|
|
`ifdef verilator
|
`ifdef verilator
|
// Function to access wb_insn (for Verilator). Have to hide this from
|
// Function to access wb_insn (for Verilator). Have to hide this from
|
// simulator, since functions with no inputs are not allowed in IEEE
|
// simulator, since functions with no inputs are not allowed in IEEE
|
| Line 416... |
Line 420... |
sel_a = `OR1200_SEL_RF;
|
sel_a = `OR1200_SEL_RF;
|
|
|
//
|
//
|
// Generation of sel_b
|
// Generation of sel_b
|
//
|
//
|
always @(rf_addrw or sel_imm or id_insn or rfwb_op or wbforw_valid or wb_rfaddrw)
|
always @(rf_addrw or sel_imm or id_insn or rfwb_op or wbforw_valid or
|
|
wb_rfaddrw)
|
if (sel_imm)
|
if (sel_imm)
|
sel_b = `OR1200_SEL_IMM;
|
sel_b = `OR1200_SEL_IMM;
|
else if ((id_insn[15:11] == rf_addrw) && rfwb_op[0])
|
else if ((id_insn[15:11] == rf_addrw) && rfwb_op[0])
|
sel_b = `OR1200_SEL_EX_FORW;
|
sel_b = `OR1200_SEL_EX_FORW;
|
else if ((id_insn[15:11] == wb_rfaddrw) && wbforw_valid)
|
else if ((id_insn[15:11] == wb_rfaddrw) && wbforw_valid)
|
| Line 431... |
Line 436... |
//
|
//
|
// Decode of multicycle
|
// Decode of multicycle
|
//
|
//
|
always @(id_insn) begin
|
always @(id_insn) begin
|
case (id_insn[31:26]) // synopsys parallel_case
|
case (id_insn[31:26]) // synopsys parallel_case
|
`ifdef UNUSED
|
|
// l.lwz
|
|
`OR1200_OR32_LWZ:
|
|
multicycle = `OR1200_TWO_CYCLES;
|
|
|
|
// l.lbz
|
|
`OR1200_OR32_LBZ:
|
|
multicycle = `OR1200_TWO_CYCLES;
|
|
|
|
// l.lbs
|
|
`OR1200_OR32_LBS:
|
|
multicycle = `OR1200_TWO_CYCLES;
|
|
|
|
// l.lhz
|
|
`OR1200_OR32_LHZ:
|
|
multicycle = `OR1200_TWO_CYCLES;
|
|
|
|
// l.lhs
|
|
`OR1200_OR32_LHS:
|
|
multicycle = `OR1200_TWO_CYCLES;
|
|
|
|
// l.sw
|
|
`OR1200_OR32_SW:
|
|
multicycle = `OR1200_TWO_CYCLES;
|
|
|
|
// l.sb
|
|
`OR1200_OR32_SB:
|
|
multicycle = `OR1200_TWO_CYCLES;
|
|
|
|
// l.sh
|
|
`OR1200_OR32_SH:
|
|
multicycle = `OR1200_TWO_CYCLES;
|
|
`endif
|
|
// l.mfspr
|
// l.mfspr
|
`OR1200_OR32_MFSPR:
|
`OR1200_OR32_MFSPR:
|
multicycle = `OR1200_TWO_CYCLES; // to read from ITLB/DTLB (sync RAMs)
|
multicycle = `OR1200_TWO_CYCLES; // to read from ITLB/DTLB (sync RAMs)
|
|
|
// ALU instructions except the one with immediate
|
|
`OR1200_OR32_ALU:
|
|
case (id_insn[3:0]) // synopsys parallel_case
|
|
4'h6: multicycle = `OR1200_MULTICYCLE_WIDTH'd3; // l.mul
|
|
4'h9: multicycle = `OR1200_MULTICYCLE_WIDTH'd2; // l.div
|
|
4'hA: multicycle = `OR1200_MULTICYCLE_WIDTH'd2; // l.divu
|
|
4'hB: multicycle = `OR1200_MULTICYCLE_WIDTH'd3; // l.mulu
|
|
default: multicycle = `OR1200_MULTICYCLE_WIDTH'd0;
|
|
endcase
|
|
`OR1200_OR32_MULI:
|
|
multicycle = `OR1200_MULTICYCLE_WIDTH'd3;
|
|
|
|
// Single cycle instructions
|
// Single cycle instructions
|
default: begin
|
default: begin
|
multicycle = `OR1200_ONE_CYCLE;
|
multicycle = `OR1200_ONE_CYCLE;
|
end
|
end
|
endcase
|
endcase
|
| Line 492... |
Line 451... |
//
|
//
|
// Encode wait_on signal
|
// Encode wait_on signal
|
//
|
//
|
always @(id_insn) begin
|
always @(id_insn) begin
|
case (id_insn[31:26]) // synopsys parallel_case
|
case (id_insn[31:26]) // synopsys parallel_case
|
|
`OR1200_OR32_ALU:
|
|
wait_on = ( 1'b0
|
|
`ifdef OR1200_DIV_IMPLEMENTED
|
|
| (id_insn[4:0] == `OR1200_ALUOP_DIV)
|
|
| (id_insn[4:0] == `OR1200_ALUOP_DIVU)
|
|
`endif
|
|
`ifdef OR1200_MULT_IMPLEMENTED
|
|
| (id_insn[4:0] == `OR1200_ALUOP_MUL)
|
|
| (id_insn[4:0] == `OR1200_ALUOP_MULU)
|
|
`endif
|
|
) ? `OR1200_WAIT_ON_MULTMAC : `OR1200_WAIT_ON_NOTHING;
|
|
`ifdef OR1200_MULT_IMPLEMENTED
|
|
`ifdef OR1200_MAC_IMPLEMENTED
|
|
`OR1200_OR32_MACMSB,
|
|
`OR1200_OR32_MACI,
|
|
`endif
|
|
`OR1200_OR32_MULI:
|
|
wait_on = `OR1200_WAIT_ON_MULTMAC;
|
|
`endif
|
|
`ifdef OR1200_MAC_IMPLEMENTED
|
|
`OR1200_OR32_MACRC:
|
|
wait_on = id_insn[16] ? `OR1200_WAIT_ON_MULTMAC :
|
|
`OR1200_WAIT_ON_NOTHING;
|
|
`endif
|
`ifdef OR1200_FPU_IMPLEMENTED
|
`ifdef OR1200_FPU_IMPLEMENTED
|
`OR1200_OR32_FLOAT: begin
|
`OR1200_OR32_FLOAT: begin
|
wait_on = id_insn[`OR1200_FPUOP_DOUBLE_BIT] ? 0 : `OR1200_WAIT_ON_FPU;
|
wait_on = id_insn[`OR1200_FPUOP_DOUBLE_BIT] ? 0 : `OR1200_WAIT_ON_FPU;
|
end
|
end
|
`endif
|
`endif
|
`ifndef OR1200_DC_WRITHROUGH
|
`ifndef OR1200_DC_WRITEHROUGH
|
// l.mtspr
|
// l.mtspr
|
`OR1200_OR32_MTSPR: begin
|
`OR1200_OR32_MTSPR: begin
|
wait_on = `OR1200_WAIT_ON_MTSPR;
|
wait_on = `OR1200_WAIT_ON_MTSPR;
|
end
|
end
|
`endif
|
`endif
|
default: begin
|
default: begin
|
wait_on = 0;
|
wait_on = `OR1200_WAIT_ON_NOTHING;
|
end
|
end
|
endcase // case (id_insn[31:26])
|
endcase // case (id_insn[31:26])
|
end // always @ (id_insn)
|
end // always @ (id_insn)
|
|
|
|
|
| Line 648... |
Line 631... |
|
|
// SFXX instructions
|
// SFXX instructions
|
`OR1200_OR32_SFXX:
|
`OR1200_OR32_SFXX:
|
sel_imm <= 1'b0;
|
sel_imm <= 1'b0;
|
|
|
`ifdef OR1200_OR32_CUST5
|
`ifdef OR1200_IMPL_ALU_CUST5
|
// l.cust5 instructions
|
// l.cust5 instructions
|
`OR1200_OR32_CUST5:
|
`OR1200_OR32_CUST5:
|
sel_imm <= 1'b0;
|
sel_imm <= 1'b0;
|
`endif
|
`endif
|
`ifdef OR1200_FPU_IMPLEMENTED
|
`ifdef OR1200_FPU_IMPLEMENTED
|
| Line 719... |
Line 702... |
`endif
|
`endif
|
`OR1200_OR32_SW,
|
`OR1200_OR32_SW,
|
`OR1200_OR32_SB,
|
`OR1200_OR32_SB,
|
`OR1200_OR32_SH,
|
`OR1200_OR32_SH,
|
`OR1200_OR32_SFXX,
|
`OR1200_OR32_SFXX,
|
`ifdef OR1200_OR32_CUST5
|
`ifdef OR1200_IMPL_ALU_CUST5
|
`OR1200_OR32_CUST5,
|
`OR1200_OR32_CUST5,
|
`endif
|
`endif
|
`OR1200_OR32_NOP:
|
`OR1200_OR32_NOP:
|
except_illegal <= 1'b0;
|
except_illegal <= 1'b0;
|
`ifdef OR1200_FPU_IMPLEMENTED
|
`ifdef OR1200_FPU_IMPLEMENTED
|
| Line 736... |
Line 719... |
except_illegal <= 1'b0
|
except_illegal <= 1'b0
|
|
|
`ifdef OR1200_MULT_IMPLEMENTED
|
`ifdef OR1200_MULT_IMPLEMENTED
|
`ifdef OR1200_DIV_IMPLEMENTED
|
`ifdef OR1200_DIV_IMPLEMENTED
|
`else
|
`else
|
| (id_insn[3:0] == `OR1200_ALUOP_DIV)
|
| (id_insn[4:0] == `OR1200_ALUOP_DIV)
|
| (id_insn[3:0] == `OR1200_ALUOP_DIVU)
|
| (id_insn[4:0] == `OR1200_ALUOP_DIVU)
|
`endif
|
`endif
|
`else
|
`else
|
| (id_insn[3:0] == `OR1200_ALUOP_DIV)
|
| (id_insn[4:0] == `OR1200_ALUOP_DIV)
|
| (id_insn[3:0] == `OR1200_ALUOP_DIVU)
|
| (id_insn[4:0] == `OR1200_ALUOP_DIVU)
|
| (id_insn[3:0] == `OR1200_ALUOP_MUL)
|
| (id_insn[4:0] == `OR1200_ALUOP_MUL)
|
`endif
|
`endif
|
|
|
`ifdef OR1200_IMPL_ADDC
|
`ifdef OR1200_IMPL_ADDC
|
`else
|
`else
|
| (id_insn[3:0] == `OR1200_ALUOP_ADDC)
|
| (id_insn[4:0] == `OR1200_ALUOP_ADDC)
|
`endif
|
`endif
|
|
|
`ifdef OR1200_IMPL_ALU_FFL1
|
`ifdef OR1200_IMPL_ALU_FFL1
|
`else
|
`else
|
| (id_insn[3:0] == `OR1200_ALUOP_FFL1)
|
| (id_insn[4:0] == `OR1200_ALUOP_FFL1)
|
`endif
|
`endif
|
|
|
`ifdef OR1200_IMPL_ALU_ROTATE
|
`ifdef OR1200_IMPL_ALU_ROTATE
|
`else
|
`else
|
| ((id_insn[3:0] == `OR1200_ALUOP_SHROT) &
|
| ((id_insn[4:0] == `OR1200_ALUOP_SHROT) &
|
(id_insn[7:6] == `OR1200_SHROTOP_ROR))
|
(id_insn[9:6] == `OR1200_SHROTOP_ROR))
|
`endif
|
`endif
|
|
|
`ifdef OR1200_IMPL_SUB
|
`ifdef OR1200_IMPL_SUB
|
`else
|
`else
|
| (id_insn[3:0] == `OR1200_ALUOP_SUB)
|
| (id_insn[4:0] == `OR1200_ALUOP_SUB)
|
|
`endif
|
|
`ifdef OR1200_IMPL_ALU_EXT
|
|
`else
|
|
| (id_insn[4:0] == `OR1200_ALUOP_EXTHB)
|
|
| (id_insn[4:0] == `OR1200_ALUOP_EXTW)
|
`endif
|
`endif
|
;
|
;
|
|
|
// Illegal and OR1200 unsupported instructions
|
// Illegal and OR1200 unsupported instructions
|
default:
|
default:
|
| Line 827... |
Line 815... |
`OR1200_OR32_SFXXI:
|
`OR1200_OR32_SFXXI:
|
alu_op <= `OR1200_ALUOP_COMP;
|
alu_op <= `OR1200_ALUOP_COMP;
|
|
|
// ALU instructions except the one with immediate
|
// ALU instructions except the one with immediate
|
`OR1200_OR32_ALU:
|
`OR1200_OR32_ALU:
|
alu_op <= id_insn[3:0];
|
alu_op <= {1'b0,id_insn[3:0]};
|
|
|
// SFXX instructions
|
// SFXX instructions
|
`OR1200_OR32_SFXX:
|
`OR1200_OR32_SFXX:
|
alu_op <= `OR1200_ALUOP_COMP;
|
alu_op <= `OR1200_ALUOP_COMP;
|
|
`ifdef OR1200_IMPL_ALU_CUST5
|
`ifdef OR1200_OR32_CUST5
|
// l.cust5
|
// l.cust5 instructions
|
|
`OR1200_OR32_CUST5:
|
`OR1200_OR32_CUST5:
|
alu_op <= `OR1200_ALUOP_CUST5;
|
alu_op <= `OR1200_ALUOP_CUST5;
|
`endif
|
`endif
|
|
|
// Default
|
// Default
|
default: begin
|
default: begin
|
alu_op <= `OR1200_ALUOP_NOP;
|
alu_op <= `OR1200_ALUOP_NOP;
|
end
|
end
|
|
|
| Line 851... |
Line 837... |
end
|
end
|
end
|
end
|
|
|
|
|
//
|
//
|
// Decode of alu_op2 (field of bits 9:8)
|
// Decode of second ALU operation field [9:6]
|
//
|
//
|
always @(posedge clk or `OR1200_RST_EVENT rst) begin
|
always @(posedge clk or `OR1200_RST_EVENT rst) begin
|
if (rst == `OR1200_RST_VALUE)
|
if (rst == `OR1200_RST_VALUE)
|
alu_op2 <= 0;
|
alu_op2 <= 0;
|
else if (!ex_freeze & id_freeze | ex_flushpipe)
|
else if (!ex_freeze & id_freeze | ex_flushpipe)
|
| Line 863... |
Line 849... |
else if (!ex_freeze) begin
|
else if (!ex_freeze) begin
|
alu_op2 <= id_insn[`OR1200_ALUOP2_POS];
|
alu_op2 <= id_insn[`OR1200_ALUOP2_POS];
|
end
|
end
|
end
|
end
|
|
|
|
|
//
|
//
|
// Decode of spr_read, spr_write
|
// Decode of spr_read, spr_write
|
//
|
//
|
always @(posedge clk or `OR1200_RST_EVENT rst) begin
|
always @(posedge clk or `OR1200_RST_EVENT rst) begin
|
if (rst == `OR1200_RST_VALUE) begin
|
if (rst == `OR1200_RST_VALUE) begin
|
| Line 938... |
Line 923... |
`else
|
`else
|
assign id_mac_op = `OR1200_MACOP_NOP;
|
assign id_mac_op = `OR1200_MACOP_NOP;
|
assign mac_op = `OR1200_MACOP_NOP;
|
assign mac_op = `OR1200_MACOP_NOP;
|
`endif
|
`endif
|
|
|
//
|
|
// Decode of shrot_op
|
|
//
|
|
always @(posedge clk or `OR1200_RST_EVENT rst) begin
|
|
if (rst == `OR1200_RST_VALUE)
|
|
shrot_op <= `OR1200_SHROTOP_NOP;
|
|
else if (!ex_freeze & id_freeze | ex_flushpipe)
|
|
shrot_op <= `OR1200_SHROTOP_NOP;
|
|
else if (!ex_freeze) begin
|
|
shrot_op <= id_insn[`OR1200_SHROTOP_POS];
|
|
end
|
|
end
|
|
|
|
//
|
//
|
// Decode of rfwb_op
|
// Decode of rfwb_op
|
//
|
//
|
always @(posedge clk or `OR1200_RST_EVENT rst) begin
|
always @(posedge clk or `OR1200_RST_EVENT rst) begin
|
| Line 1032... |
Line 1005... |
|
|
// ALU instructions except the one with immediate
|
// ALU instructions except the one with immediate
|
`OR1200_OR32_ALU:
|
`OR1200_OR32_ALU:
|
rfwb_op <= {`OR1200_RFWBOP_ALU, 1'b1};
|
rfwb_op <= {`OR1200_RFWBOP_ALU, 1'b1};
|
|
|
`ifdef OR1200_OR32_CUST5
|
`ifdef OR1200_ALU_IMPL_CUST5
|
// l.cust5 instructions
|
// l.cust5 instructions
|
`OR1200_OR32_CUST5:
|
`OR1200_OR32_CUST5:
|
rfwb_op <= {`OR1200_RFWBOP_ALU, 1'b1};
|
rfwb_op <= {`OR1200_RFWBOP_ALU, 1'b1};
|
`endif
|
`endif
|
`ifdef OR1200_FPU_IMPLEMENTED
|
`ifdef OR1200_FPU_IMPLEMENTED
|
