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//////////////////////////////////////////////////////////////////////
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//// ////
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//// OR1200's DC RAMs ////
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//// ////
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//// This file is part of the OpenRISC 1200 project ////
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//// http://opencores.org/project,or1k ////
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//// ////
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//// Description ////
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//// Instatiation of DC RAM blocks. ////
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//// ////
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//// To Do: ////
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//// - make it smaller and faster ////
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//// ////
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//// Author(s): ////
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//// - Damjan Lampret, lampret@opencores.org ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// $Log: or1200_dc_ram.v,v $
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// Revision 2.0 2010/06/30 11:00:00 ORSoC
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// Minor update:
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// Coding style changed.
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//
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// synopsys translate_off
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`include "timescale.v"
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// synopsys translate_on
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`include "or1200_defines.v"
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module or1200_dc_ram(
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// Reset and clock
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clk, rst,
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`ifdef OR1200_BIST
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// RAM BIST
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mbist_si_i, mbist_so_o, mbist_ctrl_i,
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`endif
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// Internal i/f
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addr, en, we, datain, dataout
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);
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parameter dw = `OR1200_OPERAND_WIDTH;
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parameter aw = `OR1200_DCINDX;
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//
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// I/O
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//
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input clk;
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input rst;
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input [aw-1:0] addr;
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input en;
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input [3:0] we;
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input [dw-1:0] datain;
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output [dw-1:0] dataout;
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`ifdef OR1200_BIST
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//
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// RAM BIST
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//
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input mbist_si_i;
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input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
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output mbist_so_o;
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`endif
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`ifdef OR1200_NO_DC
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//
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// Data cache not implemented
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//
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assign dataout = {dw{1'b0}};
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`ifdef OR1200_BIST
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assign mbist_so_o = mbist_si_i;
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`endif
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`else
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//
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// Instantiation of RAM block
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//
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`ifdef OR1200_DC_1W_4KB
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or1200_spram_32_bw #
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(
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.aw(10),
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.dw(32)
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)
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`endif
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`ifdef OR1200_DC_1W_8KB
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or1200_spram_32_bw #
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(
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.aw(11),
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.dw(32)
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)
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`endif
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dc_ram
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(
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`ifdef OR1200_BIST
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// RAM BIST
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.mbist_si_i(mbist_si_i),
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.mbist_so_o(mbist_so_o),
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.mbist_ctrl_i(mbist_ctrl_i),
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`endif
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.clk(clk),
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.ce(en),
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.we(we),
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.addr(addr),
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.di(datain),
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.doq(dataout)
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);
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`endif
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endmodule // or1200_dc_ram
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