OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [or1200/] [or1200_dc_ram.v] - Diff between revs 360 and 476

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 360 Rev 476
Line 116... Line 116... 
     (
 
     (
 
      .aw(11),
 
      .aw(11),
 
      .dw(32)
 
      .dw(32)
 
      )
 
      )
 
`endif
 
`endif
 
 
 
`ifdef OR1200_DC_1W_16KB
 
 
 
   or1200_spram_32_bw #
 
 
 
     (
 
 
 
      .aw(12),
 
 
 
      .dw(32)
 
 
 
      )
 
 
 
`endif
 
   dc_ram
 
   dc_ram
 
     (
 
     (
 
`ifdef OR1200_BIST
 
`ifdef OR1200_BIST
 
      // RAM BIST
 
      // RAM BIST
 
      .mbist_si_i(mbist_si_i),
 
      .mbist_si_i(mbist_si_i),

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.