URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [or1200/] [or1200_dc_ram.v] - Diff between revs 482 and 483

Show entire file | Details | Blame | View Log

Rev 482	Rev 483
Line 59...	Line 59...

`ifdef OR1200_BIST	`ifdef OR1200_BIST
`// RAM BIST`	`// RAM BIST`
`mbist_si_i, mbist_so_o, mbist_ctrl_i,`	`mbist_si_i, mbist_so_o, mbist_ctrl_i,`
`endif	`endif
	`ifdef OR1200_RAM_PARITY
	`// Parity error indicator`
	`p_err,`
	`endif
`// Internal i/f`	`// Internal i/f`
`addr, en, we, datain, dataout`	`addr, en, we, datain, dataout`

`);`	`);`

parameter dw = `OR1200_OPERAND_WIDTH;	parameter dw = `OR1200_OPERAND_WIDTH;
parameter aw = `OR1200_DCINDX;	parameter aw = `OR1200_DCINDX;

Line 77...	Line 81...
`input [aw-1:0] addr;`	`input [aw-1:0] addr;`
`input en;`	`input en;`
`input [3:0] we;`	`input [3:0] we;`
`input [dw-1:0] datain;`	`input [dw-1:0] datain;`
`output [dw-1:0] dataout;`	`output [dw-1:0] dataout;`
	`ifdef OR1200_RAM_PARITY
	`output p_err;`
	`endif


`ifdef OR1200_BIST	`ifdef OR1200_BIST
`//`	`//`
`// RAM BIST`	`// RAM BIST`
`//`	`//`
Line 96...	Line 104...
`//`	`//`
`assign dataout = {dw{1'b0}};`	`assign dataout = {dw{1'b0}};`
`ifdef OR1200_BIST	`ifdef OR1200_BIST
`assign mbist_so_o = mbist_si_i;`	`assign mbist_so_o = mbist_si_i;`
`endif	`endif
	`ifdef OR1200_RAM_PARITY
	`assign p_err = 0;`
	`endif

`else	`else

`//`	`//`
`// Instantiation of RAM block`	`// Instantiation of RAM block`
Line 107...	Line 118...
`or1200_spram_32_bw #`	`or1200_spram_32_bw #`
`(`	`(`
.aw(`OR1200_DCINDX),	.aw(`OR1200_DCINDX),
`.dw(dw)`	`.dw(dw)`
`)`	`)`
`dc_ram`	`dc_ram0`
`(`	`(`
`ifdef OR1200_BIST	`ifdef OR1200_BIST
`// RAM BIST`	`// RAM BIST`
`.mbist_si_i(mbist_si_i),`	`.mbist_si_i(mbist_si_i),`
`.mbist_so_o(mbist_so_o),`	`.mbist_so_o(mbist_so_o),`
`.mbist_ctrl_i(mbist_ctrl_i),`	`.mbist_ctrl_i(mbist_ctrl_i),`
`endif	`endif
	`ifdef OR1200_RAM_PARITY
	`.p_err(p_err),`
	`endif
`.clk(clk),`	`.clk(clk),`
	`.rst(rst),`
`.ce(en),`	`.ce(en),`
`.we(we),`	`.we(we),`
`.addr(addr),`	`.addr(addr),`
`.di(datain),`	`.di(datain),`
`.doq(dataout)`	`.doq(dataout)`
`ifdef OR1200_RAM_PARITY
`, .p_err()`
`endif
`);`	`);`
`endif	`endif

`endmodule // or1200_dc_ram`	`endmodule // or1200_dc_ram`

`No newline at end of file`	`No newline at end of file`

Browse

Tools

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [or1200/] [or1200_dc_ram.v] - Diff between revs 482 and 483