URL
https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk
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Rev 476 |
Rev 477 |
Line 106... |
Line 106... |
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//
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//
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// Instantiation of TAG RAM block
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// Instantiation of TAG RAM block
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//
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//
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// Data widths are tag width plus one for valid
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// Data widths are tag width plus one for valid
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`ifdef OR1200_DC_1W_4KB
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or1200_spram #
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or1200_spram #
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(
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(
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.aw(8),
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.aw(`OR1200_DCTAG),
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.dw(`OR1200_DCTAG_W + 1)
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.dw(`OR1200_DCTAG_W + 1)
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)
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)
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`endif
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`ifdef OR1200_DC_1W_8KB
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or1200_spram #
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(
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.aw(9),
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.dw(`OR1200_DCTAG_W + 1)
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)
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`endif
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`ifdef OR1200_DC_1W_16KB
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or1200_spram #
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(
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.aw(10),
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.dw(`OR1200_DCTAG_W + 1)
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)
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`endif
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dc_tag0
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dc_tag0
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(
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(
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`ifdef OR1200_BIST
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`ifdef OR1200_BIST
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// RAM BIST
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// RAM BIST
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.mbist_si_i(mbist_si_i),
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.mbist_si_i(mbist_si_i),
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