| Line 59... |
Line 59... |
`ifdef OR1200_BIST
|
`ifdef OR1200_BIST
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// RAM BIST
|
// RAM BIST
|
mbist_si_i, mbist_so_o, mbist_ctrl_i,
|
mbist_si_i, mbist_so_o, mbist_ctrl_i,
|
`endif
|
`endif
|
|
|
|
`ifdef OR1200_RAM_PARITY
|
|
// Parity error indicator
|
|
p_err,
|
|
`endif
|
|
|
// Internal i/f
|
// Internal i/f
|
addr, en, we, datain, tag_v, tag, dirty
|
addr, en, we, datain, tag_v, tag, dirty
|
);
|
);
|
|
|
parameter dw = `OR1200_DCTAG_W+1;
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parameter dw = `OR1200_DCTAG_W+1;
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| Line 88... |
Line 93... |
//
|
//
|
input mbist_si_i;
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input mbist_si_i;
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input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
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input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
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output mbist_so_o;
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output mbist_so_o;
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`endif
|
`endif
|
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`ifdef OR1200_RAM_PARITY
|
|
parameter tag_ram_extra_width = 24 - (`OR1200_DCTAG_W+1);
|
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output p_err;
|
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wire [24-3:0] tag_wire;
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`else
|
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wire [dw-3:0] tag_wire;
|
|
`endif
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|
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`ifdef OR1200_NO_DC
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`ifdef OR1200_NO_DC
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|
|
//
|
//
|
// Data cache not implemented
|
// Data cache not implemented
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| Line 100... |
Line 112... |
assign tag_v = 1'b0;
|
assign tag_v = 1'b0;
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`ifdef OR1200_BIST
|
`ifdef OR1200_BIST
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assign mbist_so_o = mbist_si_i;
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assign mbist_so_o = mbist_si_i;
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`endif
|
`endif
|
|
|
|
`ifdef OR1200_RAM_PARITY
|
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assign p_err = 0;
|
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`endif
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|
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`else
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`else
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|
|
assign tag = tag_wire[dw-3:0];
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|
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//
|
//
|
// Instantiation of TAG RAM block
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// Instantiation of TAG RAM block
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//
|
//
|
// Data widths are tag width plus one for valid
|
// Data widths are tag width plus one for valid
|
or1200_spram #
|
or1200_spram #
|
(
|
(
|
.aw(`OR1200_DCTAG),
|
.aw(`OR1200_DCTAG),
|
|
`ifdef OR1200_RAM_PARITY
|
|
.dw(24)
|
|
`else
|
.dw(`OR1200_DCTAG_W + 1)
|
.dw(`OR1200_DCTAG_W + 1)
|
|
`endif
|
)
|
)
|
dc_tag0
|
dc_tag0
|
(
|
(
|
`ifdef OR1200_BIST
|
`ifdef OR1200_BIST
|
// RAM BIST
|
// RAM BIST
|
.mbist_si_i(mbist_si_i),
|
.mbist_si_i(mbist_si_i),
|
.mbist_so_o(mbist_so_o),
|
.mbist_so_o(mbist_so_o),
|
.mbist_ctrl_i(mbist_ctrl_i),
|
.mbist_ctrl_i(mbist_ctrl_i),
|
`endif
|
`endif
|
.clk(clk),
|
.clk(clk),
|
|
.rst(rst),
|
.ce(en),
|
.ce(en),
|
.we(we),
|
.we(we),
|
.addr(addr),
|
.addr(addr),
|
.di(datain),
|
|
.doq({tag, tag_v, dirty})
|
|
`ifdef OR1200_RAM_PARITY
|
`ifdef OR1200_RAM_PARITY
|
, .p_err()
|
.p_err(p_err),
|
|
.di({{tag_ram_extra_width{1'b0}},datain}),
|
|
`else
|
|
.di(datain),
|
`endif
|
`endif
|
|
.doq({tag_wire, tag_v, dirty})
|
);
|
);
|
`endif
|
`endif
|
|
|
endmodule // or1200_dc_tag
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endmodule // or1200_dc_tag
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No newline at end of file
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No newline at end of file
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